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make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
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speculative load/store pipelines can reenable this
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calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
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Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
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define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
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segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
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remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
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Also, match the resPool event function names to the cpu event function names
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once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
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once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
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also, cleanup comments for gem5.fast compilation
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dont treat read() and write() fields as mut. exclusive
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only update BTB on a taken branch and update branch predictor w/pcstate from instruction
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only pay attention to branch predictor updates if the the inst. is in fact a branch
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define separate priority resource pool squash and graduate events
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this causes forwarding a bad value register value
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use it in reg. dep. tracking
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dont use offset to calculate this but rather an enum
that can be updated
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implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
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valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
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The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
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formerly, this was implicit when you accessed the execution unit
or the use-def unit but it's better that this just be something
that a user can specify.
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add find and end functions for inst. schedules
that can search by stage number
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keep stats for int/float reg file usage instead
of aggregating across reg file types
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make handling of speculative and nonspeculative insts
more explicit
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Architectures like SPARC need to read the window pointer
in order to figure out it's register dependence. However,
this may not get updated until after an instruction gets
executed, so now we lazily detect the register dependence
in the EXE stage (execution unit or use_def). This
makes sure we get the mapping after the most current change.
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provide a sanity check for someone coding
a new architecture
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call trap function when a fault is received
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ignore writes to the ISA zero register
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get rid of accessing iterators (for instructions) by reference
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clean up control flow to make it easier to understand
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- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
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since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
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After a checkpoint we need to make sure that we restore the right
number of entries.
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Instead of clearing the entire TLB on initialization and flush, the code was
clearing only one element. This patch corrects the memsets in the init and
flush routines.
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The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.
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If there's a problem when reading the section names from a supposed ELF file,
this change makes gem5 print an error message as returned by libelf and die.
Previously these sorts of errors would make gem5 segfault when it tried to
access the section name through a NULL pointer.
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this flag is only used for early branch resolution in the O3 model (of pc-relative branches)
but this isnt cleanly working even when the branch target code is added for sparc. For now,
we'll ignore this optimization and add a todo in the SPARC ISA for future developers
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Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
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