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AgeCommit message (Expand)Author
2018-05-08mem-cache: Create block insertion functionDaniel R. Carvalho
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
2018-05-08dev: Add support for a simple debug UARTAndreas Sandberg
2018-05-03mem-ruby: Consistent dprintf formats for issue outcomesBrad Beckmann
2018-05-03arch-x86: Enable fstatfs for x86_64Tony Gutierrez
2018-05-03mem-cache: Create Second-Chance replacement policyDaniel R. Carvalho
2018-05-03mem-cache: ReplacementPolicy specific replacement dataDaniel R. Carvalho
2018-05-02arch-x86: implement movntps/movntpd SSE instsSteve Reinhardt
2018-05-02x86: Add a ld/st microop flag for marking an access uncacheable.Gabe Black
2018-05-02arch-x86: Enable the umask system callTony Gutierrez
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-04-26mem-cache: Use block iteration in BaseSetAssocDaniel R. Carvalho
2018-04-20docs: Fix power model doxygenJason Lowe-Power
2018-04-19mem-cache: Use findBlock in FALRU's block accessDaniel R. Carvalho
2018-04-19mem-cache: Use secure flag in FALRU's findBlockDaniel R. Carvalho
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
2018-04-18mem-cache: Create NRU Replacement PolicyDaniel R. Carvalho
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-18mem-cache: Revamp multiple size tracking for FALRU cachesNikos Nikoleris
2018-04-18dev, arm: Cleanup Pl050 interrupt handlingAndreas Sandberg
2018-04-17gpu-compute: fix bad asserts in gpu tlb and cu tlb portTony Gutierrez
2018-04-17mem-ruby: enable DPRINTFN calls in slicc for temporary debug printingJohn Alsop
2018-04-17arch-arm: Fix secure MiscReg access when EL3 is not AArch32Giacomo Travaglini
2018-04-17ps2: Unify constant namesAndreas Sandberg
2018-04-17dev, arm: Use the PS/2 framework in the Pl050 modelAndreas Sandberg
2018-04-17ps2: Add proper touchscreen command handlingAndreas Sandberg
2018-04-17ps2: Implement the keyboard reset commandAndreas Sandberg
2018-04-17ps2: Unify device data bufferingAndreas Sandberg
2018-04-17ps2: Add a simple touchscreen modelAndreas Sandberg
2018-04-17ps2: Add VNC support to the keyboard modelAndreas Sandberg
2018-04-17ps2: Factor out PS/2 devices into their own subsystemAndreas Sandberg
2018-04-17mem: Add a helper function to get a word of variable lengthAndreas Sandberg
2018-04-13ruby,gpu-compute: bugfix for GPU_VIPER* protocolsBrandon Potter
2018-04-13ruby: bugfix for MESI_Three_Level protocolBrandon Potter
2018-04-13mem-ruby: fix more style issues in AMD licensesTony Gutierrez
2018-04-13mem-cache: Add MoveToTail to FALRUDaniel R. Carvalho
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
2018-04-10dev: arm: SetScaling commands don't send parameter bytes.Gabe Black
2018-04-06arch: alpha: Fix an 8 year old bug from the transition to pc objects.Gabe Black
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
2018-04-06arch-arm: Fix AArch32 branch instructions disassembleGiacomo Travaglini
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