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AgeCommit message (Expand)Author
2012-07-22X86 CPUID: Return false if unknown processor familyNilay Vaish
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11x86: added page size in bytes tlb entry functionBrad Beckmann
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10syscall emulation: Add the futex system call.Marc Orr
2012-07-10x86: logSize and lruSeq are now optional ckpt paramsBrad Beckmann
2012-07-10Add hook to call map() on Process from python.Steve Reinhardt
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10imported patch jason/slicc-external-structure-fixBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10cpu: added assertions to ensure the correct proxies are usedBrad Beckmann
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-07-09EventManager: Rename queue accessor and remove cast operatorAndreas Hansson
2012-07-09Mem: Make members relating to range and size constantAndreas Hansson
2012-07-09Port: Hide the queue implementation in SimpleTimingPortAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add getAddrRanges to master port (asking slave port)Andreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-07-02gcc: Fix warnings for gcc 4.7 and clang 3.1Andreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Mem: Fix a livelock resulting in LLSC/locked memory access implementation.Matt Evans
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-29ARM: Update version of linux we claim to be to 3.0.0.Ali Saidi
2012-06-29ARM: Fix issue with predicted next pc being wrong because of advance() ordering.Ali Saidi
2012-06-27ARM: Fix address range issue with VExpress EMMAli Saidi
2012-06-11ARM: implement the ProcessInfo methodsAnthony Gutierrez
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-06-08Power: Fix MaxMiscDestRegs which was set to zeroAndreas Hansson
2012-06-07X86 TLB: Add a missing = signNilay Vaish
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-07X86 TLB: Fix for gcc 4.4.3Jayneel Gandhi
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez