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Age
Commit message (
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Author
2008-03-25
Fix handling of writeback-induced writebacks in atomic mode.
Steve Reinhardt
2008-03-24
Delete the Request for a no-response Packet
Steve Reinhardt
2008-03-24
Don't FastAlloc MSHRs since we don't allocate them on the fly.
Steve Reinhardt
2008-03-24
Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.
Steve Reinhardt
2008-03-22
Fix cache problem with writes to tempBlock
Steve Reinhardt
2008-03-20
MIPS: Check endianness of binaries in SE mode.
Gabe Black
2008-03-17
Fix a few Packet memory leaks.
Steve Reinhardt
2008-03-17
Restructure bus timing calcs to cope with pkt being deleted by target.
Steve Reinhardt
2008-03-15
Fix subtle cache bug where read could return stale data
Steve Reinhardt
2008-03-06
Merge
Gabe Black
2008-03-06
X86: Refine the local APIC.
Gabe Black
2008-03-06
O3CPU: Don't call dumpInsts if DEBUG is not defined
Vilas Sridharan
2008-03-01
X86: Don't map the local APIC into the physical address space in SE mode.
Gabe Black
2008-02-27
Automated merge with ssh://daystrom.m5sim.org//repo/m5
Steve Reinhardt
2008-02-27
Add comments in code to describe bug conditions.
Korey Sewell
2008-02-27
Fix Load/Store Queue squashing after a SMT thread is removed but ensuring
Korey Sewell
2008-02-27
Fix offset in removeThread() function so that float registers start freeing up
Korey Sewell
2008-02-26
Revamp cache timing access mshr check to make stats sane again.
Steve Reinhardt
2008-02-27
Configs: Make using Simpoints easier with some config files that support them...
Rick Strong
2008-02-26
X86: Put in initial implementation of the local APIC.
Gabe Black
2008-02-26
X86: Implement the INVLPG instruction and the TIA microop.
Gabe Black
2008-02-26
TLB: Make a TLB base class and put a virtual demapPage function in it.
Gabe Black
2008-02-26
X86: Get PCI config space to work, and adjust address space prefix numbering ...
Gabe Black
2008-02-26
Cache: better comments particularly regarding writeback situation.
Steve Reinhardt
2008-02-26
Bus: Fix the bus timing to be more realistic.
Gabe Black
2008-02-16
Make L2+ caches allocate new block for writeback misses
Steve Reinhardt
2008-02-14
CPU: move the PC Events code to a place where the code won't be executed mult...
Ali Saidi
2008-02-11
Update copyright dates
Ali Saidi
2008-02-11
Automated merge with file:/home/stever/hg/m5-orig
Steve Reinhardt
2008-02-11
EXTRAS now points to src instead of needing 'src' subdir.
Steve Reinhardt
2008-02-10
Bus: Only update port cache when there is an item to update it with.
Nicolas Zea
2008-02-10
IGbE: Fix a couple of bugs.
Ali Saidi
2008-02-10
Fix #include lines for renamed cache files.
Steve Reinhardt
2008-02-10
Rename cache files for brevity and consistency with rest of tree.
Steve Reinhardt
2008-02-06
Make the Event::description() a const function
Stephen Hines
2008-02-05
Add base ARM code to M5
Stephen Hines
2008-02-05
Cleaned up os.path imports a bit.
Steve Reinhardt
2008-02-05
Make EXTRAS work for SConsopts too.
Steve Reinhardt
2008-01-23
X86: Put an SMBios/DMI table in memory.
Gabe Black
2008-01-23
X86: Optomize the bit scanning instruction microassembly a little. More can b...
Gabe Black
2008-01-22
X86: Implement and attach the BSR and BSF instructions.
Gabe Black
2008-01-21
X86: Fill out group17 in the decoder.
Gabe Black
2008-01-21
X86: Use the existing boot_osflags instead of duplicating it.
Gabe Black
2008-01-14
The reason is that the event is supposed to put the instructions ready to exe...
Ke Meng
2008-01-12
X86: Redo the bit test instructions.
Gabe Black
2008-01-12
X86: Fix the wrmsr instruction.
Gabe Black
2008-01-12
X86: Make the effective segment base shadow the regular one, not the selector.
Gabe Black
2008-01-12
X86: Make the IO ports work using extra physical address lines. Add a serial ...
Gabe Black
2008-01-12
X86: Fix the general IO instructions dataSize.
Gabe Black
2008-01-06
Temporary fix for ll/sc bug see flyspray task for more info:
Geoffrey Blake
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