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AgeCommit message (Expand)Author
2008-06-12X86: Add microops which panic, fatal, warn, and warn_once.Gabe Black
2008-06-12X86: Truncate descriptors to 16 bits.Gabe Black
2008-06-12X86: Redo BSF.Gabe Black
2008-06-12X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.Gabe Black
2008-06-12X86: Make string instructions work when rcx=0.Gabe Black
2008-06-12X86: Have all 8 machine check registers since the kernel assumes they're there.Gabe Black
2008-06-12X86: Bypass unaligned access support for register addressed MSRs.Gabe Black
2008-06-12X86: Remove enforcement of APIC register access alignment. Panic if more than...Gabe Black
2008-06-12X86: Fix the implementation of BSF.Gabe Black
2008-06-12X86: Bit scan forward/reverse were accidentally transposed.Gabe Black
2008-06-12X86: Fix a byte register indexing issue in the sign extending move from memor...Gabe Black
2008-06-12X86: Add in some support for the tsc register.Gabe Black
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-06-11X86: Fix building on *BSD hostsAli Saidi
2008-06-11SCons: Fix more SCons version issuesAli Saidi
2008-05-20IGbE: Implement sending packet that is contained in more than 2 descriptors.Ali Saidi
2008-05-20SCons: Fixing SCons bug 2006 issues for non-alpha ISAsStephen Hines
2008-05-15Make sure that output files are always checked success before they're used.Ali Saidi
2008-05-06SCons: More scons fixing for SCons bug 2006Ali Saidi
2008-04-10SCons: add comments to SConscript documenting bug workaroundAli Saidi
2008-04-10PhysicalMemory: Add parameter for variance in memory delay.Ali Saidi
2008-04-08SCons: Manually specifying header only directories with Dir() works around th...Ali Saidi
2008-03-25IGbE: Fix bug that limits wire performance a bitAli Saidi
2008-03-25Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
2008-03-25Fix handling of writeback-induced writebacks in atomic mode.Steve Reinhardt
2008-03-25X86: Put an RTC into the CMOS part of the southbridge.Gabe Black
2008-03-25Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.Gabe Black
2008-03-25X86: Turn #defines into consts.Gabe Black
2008-03-25X86: Start implementing the south bridge stuff.Gabe Black
2008-03-25X86: Change the Opteron platform to be the PC platform.Gabe Black
2008-03-24Delete the Request for a no-response PacketSteve Reinhardt
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
2008-03-24Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.Steve Reinhardt
2008-03-22Fix cache problem with writes to tempBlockSteve Reinhardt
2008-03-20MIPS: Check endianness of binaries in SE mode.Gabe Black
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
2008-03-06MergeGabe Black
2008-03-06X86: Refine the local APIC.Gabe Black
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
2008-03-01X86: Don't map the local APIC into the physical address space in SE mode.Gabe Black
2008-02-27Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
2008-02-27Configs: Make using Simpoints easier with some config files that support them...Rick Strong
2008-02-26X86: Put in initial implementation of the local APIC.Gabe Black
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
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