gem5 - gem5

Age	Commit message (Expand)	Author
2007-11-15	fix MIPS headers	Korey Sewell
2007-11-15	add core specific parameter to BaseCPU params	Korey Sewell
2007-11-15	Add CoreSpecific type to all archs	Korey Sewell
2007-11-15	Get MIPS simple regression working. Take out unecessary functions "setShadowS...	Korey Sewell
2007-11-15	branch merge	Korey Sewell
2007-11-14	Checkpointing: Name SE page table entries better so that there isn't a proble...	Ali Saidi
2007-11-14	comment and spacing	Korey Sewell
2007-11-14	Get MIPS_SE actually working again by actually by fixing TLB stuff and runnin...	Korey Sewell
2007-11-14	remove unnecessary debug messages I added	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-11-13	X86: Make microcode use presegmentation RIPs and the rest of m5 use post segm...	Gabe Black
2007-11-12	X86: Separate out the page table walker into it's own cc and hh.	Gabe Black
2007-11-12	Params: Fix check for cycles in the configuration and clarify the comments/er...	Gabe Black
2007-11-12	X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug s...	Gabe Black
2007-11-12	X86: Implement tlb invalidation and make it happen some of the times it should.	Gabe Black
2007-11-12	X86: Implement the wrcr microop which writes a control register, and some con...	Gabe Black
2007-11-12	X86: Implement some bit testing instructions.	Gabe Black
2007-11-12	X86: Change the meaning of the sext and zext width operand, and make sext set...	Gabe Black
2007-11-12	X86: Flesh out the opcode groups for two byte opcodes.	Gabe Black
2007-11-12	X86: Work on the page table walker, TLB, and related faults.	Gabe Black
2007-11-12	X86: Implement a page table walker.	Gabe Black
2007-11-12	X86: Make the micropc available through the thread context objects.	Gabe Black
2007-11-12	X86: Implement the startupCPU function.	Gabe Black
2007-11-12	X86: Make some of the bits of CR0 do what they're supposed to.	Gabe Black
2007-11-12	X86: Various fixes to indexing segmentation related registers	Gabe Black
2007-11-11	SPARC: Force %g1 to be zero on process startup even though it normally alread...	Gabe Black
2007-11-08	Alpha: Fix a long standing bug where all code ran as PAL code in FS.	Gabe Black
2007-11-08	Make non Apple compilation work again. Ali may have to refix this.	Gabe Black
2007-11-08	ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.	Gabe Black
2007-11-08	Compiling: Fix for 64bit compile on Darwin/OSX 10.5.	Ali Saidi
2007-11-08	TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.	Ali Saidi
2007-11-08	AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.	Ali Saidi
2007-11-08	Python: Allow a range to be a python tuple/list.	Ali Saidi
2007-11-08	Interrupts: Inline some code and remove duplication.	Ali Saidi
2007-11-08	CPU: Add function to explictly compare thread contexts after copying.	Ali Saidi
2007-11-07	SPARC: Make 64 bit SPARC process initialization check checkpointRestored too.	Gabe Black
2007-11-06	O3: Remove unneeded variable.	Gabe Black
2007-11-04	TraceFlags: Fix off-by-one error with number of traceflags.	Ali Saidi
2007-11-04	Cache: Fix for OS X 10.5 compiling.	Ali Saidi
2007-11-02	SE: fix stat64 syscall on os x	Ali Saidi
2007-11-01	DRAM: Make latency parameters be Param.Latency instead of ints.	Ali Saidi
2007-10-31	String constant const-ness changes to placate g++ 4.2.	Steve Reinhardt
2007-10-31	no manual changes	Ali Saidi
2007-10-31	Traceflags: Old traceflags.py file is no longer needed.	Ali Saidi
2007-10-31	Merge in bus DPRINTF changes.	Steve Reinhardt
2007-10-31	Traceflags: Add SCons function to created a traceflag instead of having one f...	Ali Saidi
2007-10-31	Linux Support: Finally update vptr for new memory system.	Ali Saidi
2007-10-31	Base: Rework the way M5 provides and creates random numbers.	Ali Saidi
2007-10-30	Add constant stat.	Vilas Sridharan
2007-10-30	X86: Compile fixes for 32 bit/debug/opt.	Gabe Black