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AgeCommit message (Expand)Author
2016-12-21cpu: correct comments in tournament branch predictorArthur Perais
2016-12-21cpu: Resolve targets of predicted 'taken' decode for O3Arthur Perais
2016-12-21cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3Arthur Perais
2016-12-20ruby: Make MessageBuffers actually finite sizedJoel Hestness
2016-12-20ruby: fix typo in DMASequencer::ackCallback()Tony Gutierrez
2016-12-20ruby: fix issue with unused var in DMASequencerTony Gutierrez
2016-12-19arm: provide correct timer availability in ID_PFR1 registerCurtis Dunham
2016-12-19arm: compute ID_AA64PFR{0,1}_EL1 registersCurtis Dunham
2016-12-19arm: compute ID_PFR{0,1} registersCurtis Dunham
2016-12-19arm: miscreg refactoringCurtis Dunham
2016-12-19arm: audit SCTLRCurtis Dunham
2016-12-19arm: remove SCTLR.FICurtis Dunham
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-12-19mem: Make the BaseXBar public to not confuse Python wrappersAndreas Sandberg
2016-12-19python: Export periodicStatDumpAndreas Sandberg
2016-12-19dev: Include DmaDevice in NULL buildsAndreas Sandberg
2016-12-19python: Fix incorrect header in the DmaDevice wrapperAndreas Sandberg
2016-12-19sim: Remove redundant buildEnv importAndreas Sandberg
2016-12-15ruby: Detect garnet network-level deadlock.Jieming Yin
2016-11-09base: remove header file to prevent a macro name collisionBrandon Potter
2016-12-15syscall_emul: implement fallocateBrandon Potter
2016-12-15syscall_emul: add support for x86 statfs system callsBrandon Potter
2016-12-15syscall_emul: extend sysinfo system call to include mem_unitBrandon Potter
2016-12-06dev: Fix race conditions at terminating dist-gem5 simulationsGabor Dozsa
2016-12-05ruby: Remove RubyMemoryControl and associated filesAndreas Hansson
2016-12-05mem: Respond to InvalidateReq when the block is (pending) dirtyNikos Nikoleris
2016-12-05mem: Invalidate a blk when servicing the 1st invalidating targetNikos Nikoleris
2016-12-05mem: Allow non invalidating snoops on an InvalidateReq MSHRNikos Nikoleris
2016-12-05mem: Don't use hasSharers in the snoopFilter for memory responsesNikos Nikoleris
2016-12-05mem: Always use InvalidateReq to service WriteLineReq missesNikos Nikoleris
2016-12-05mem: Assert that the responderHadWritable is set only onceNikos Nikoleris
2016-12-05mem: Ensure InvalidateReq is considered isForward by MSHRsAndreas Hansson
2016-12-05mem: Make packet debug printing more uniformNikos Nikoleris
2016-12-05cpu: Change traffic generators to use different values for writesNikos Nikoleris
2016-12-05mem: Service only the 1st FromCPU MSHR target on ReadRespWithInvNikos Nikoleris
2016-12-05mem: Keep track of allocOnFill in the TargetListNikos Nikoleris
2016-12-05mem: Add support for repopulating the flags of an MSHR TargetListNikos Nikoleris
2016-12-02hsail: disable asserts to allow immediate operands i.e. 0 with loadsBrandon Potter
2016-12-02hsail: add stub type and stub out several instructionsBrandon Potter
2016-12-02hsail: add popcount type and generate popcount instructionsBrandon Potter
2016-12-02hsail: add a wavesize case statement to register operand codeBrandon Potter
2016-12-02hsail: generate mov instructions for more arith_types and bit_typesBrandon Potter
2016-12-02hsail: remove the panic guarding function directivesBrandon Potter
2016-12-02hsail: fix unsigned offset bug in address calculationTony Gutierrez
2016-12-02ruby: Fix overflow reported by ASAN in MessageBuffer.Matthew Poremba
2016-11-30riscv: [Patch 7/5] Corrected LRSC semanticsAlec Roelke
2016-11-30riscv: [Patch 6/5] Improve Linux emulation for RISC-VAlec Roelke
2016-11-30riscv: [Patch 5/5] Added missing support for timing CPU modelsAlec Roelke
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke