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Age
Commit message (
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Author
2013-04-23
cpu: Fix TraceGen flag initalisation
Andreas Hansson
2013-04-23
ruby: mesi coherence protocol: remove unused state M_MB
Nilay Vaish
2013-04-23
x86: increment the stack pointer in lret inst
Christian Menard
2013-04-23
ruby: patch checkpoint restore with garnet
Nilay Vaish
2013-04-22
mem: Address mapping with fine-grained channel interleaving
Andreas Hansson
2013-04-22
mem: More descriptive enum names for address mapping
Andreas Hansson
2013-04-22
cpu: Use request flags in trace playback
Andreas Hansson
2013-04-22
cpu: Make the generators usable outside the TrafficGen module
Andreas Hansson
2013-04-22
mem: Add a WideIO DRAM configuration
Andreas Hansson
2013-04-22
mem: Adding verbose debug output in the memory system
Uri Wiener
2013-04-22
mem: Replace check with panic where inhibited should not happen
Andreas Hansson
2013-04-22
kvm: Add support for pseudo-ops on ARM
Andreas Sandberg
2013-04-22
sim: Add a helper function to execute pseudo instructions
Andreas Sandberg
2013-04-22
kvm: Add support for state dumping on ARM
Andreas Sandberg
2013-04-22
kvm: Add basic support for ARM
Andreas Sandberg
2013-04-22
arm: Add a method to query interrupt state ignoring CPSR masks
Andreas Sandberg
2013-04-22
kvm: Add experimental support for a perf-based execution timer
Andreas Sandberg
2013-04-22
kvm: Avoid synchronizing the TC on every KVM exit
Andreas Sandberg
2013-04-22
kvm: Basic support for hardware virtualized CPUs
Andreas Sandberg
2013-04-22
cpu: Let python scripts obtain the number of instructions executed
Timothy M. Jones
2013-04-22
arm: Enable support for triggering a sim panic on kernel panics
Andreas Sandberg
2013-04-22
sim: separate nextCycle() and clockEdge() in clockedObjects
Dam Sunwoo
2013-04-22
cpu: generate SimPoint basic block vector profiles
Dam Sunwoo
2013-04-22
ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.
Chris Emmons
2013-04-22
sim: Add helper functions that add PCEvents with custom arguments
Andreas Sandberg
2013-04-22
cpu: fix a switching issue with the o3 cpu.
Ali Saidi
2013-04-17
Merged c22628fa2564 and 2285b98847d7
Nilay Vaish
2013-04-17
base: load weak symbols from object file
Deyuan Guo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-04-17
arm: set ldr_ret_uop as conditional or unconditional control
Nathanael Premillieu
2013-04-17
ruby: moesi cmp directory: add copyright notice
Nilay Vaish
2013-04-17
dev: Fix a bug in the use of seekp/seekg
Andreas Hansson
2013-04-09
Ruby: Fix RubyPort evict packet memory leak
Joel Hestness
2013-04-09
Ruby: Delete packet requests during warmup
Joel Hestness
2013-04-09
Ruby: Add field to slicc machine for generic type
Joel Hestness
2013-04-09
Ruby: Order profilers based on version
Joel Hestness
2013-04-09
Ruby: More descriptive message buffer connection fatal
Jason Power
2013-04-09
Ruby: Fix typo in Slicc if-statement AST error
Jason Power
2013-04-07
Ruby System, Cache Recorder: Use delete [] for trace vars
Joel Hestness
2013-03-29
o3cpu: commit: changes interrupt handling
Nilay Vaish
2013-03-28
x86: changes to apic, keyboard
Nilay Vaish
2013-03-27
mem: Fix cache latency bug
Mitch Hayenga
2013-03-27
scons: don't die on warnings in swig-generated code
Steve Reinhardt
2013-03-26
mem: Cancel cache retry event when blocking port
Rene de Jong
2013-03-26
mem: Separate waiting for the bus and waiting for a peer
Andreas Hansson
2013-03-26
mem: Introduce a variable for the retrying port
Andreas Hansson
2013-03-26
mem: Add a generic id field to the packet trace
Andreas Hansson
2013-03-26
mem: Add optional request flags to the packet trace
Andreas Hansson
2013-03-26
cpu: Remove CpuPort and use MasterPort in the CPU classes
Andreas Hansson
2013-03-22
ruby: slicc: set sender, receiver clock objs for optional queue
Nilay Vaish
2013-03-22
ruby: message buffer: correct previous errors
Nilay Vaish
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