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AgeCommit message (Expand)Author
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
2017-12-06base: Split out the pixel class in framebuffer.(cc|hh).Gabe Black
2017-12-06base: Handle zero fill in cprintf when printing floats.Gabe Black
2017-12-06tests: Fix the source file for the cprintftime test.Gabe Black
2017-12-06scons: Several fixes having to do with tags and sets.Gabe Black
2017-12-06scons: Track and reuse object nodes for a given source file.Gabe Black
2017-12-05x86: LOOP's operand size defaults to 64 bits in 64 bit mode.Gabe Black
2017-12-05learning-gem5: Fix missing misc.hh in hello_object.ccHanhwi Jang
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
2017-12-05mem-ruby: Prevent ruby from crashing on CMOsNikos Nikoleris
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
2017-12-05mem: Ignore clean requests in the abstract memoryNikos Nikoleris
2017-12-05mem: Handle CMO responses in the snoop filterNikos Nikoleris
2017-12-05mem: Allow CMOs as snooping requests in the snoop filterNikos Nikoleris
2017-12-05mem: Co-ordination of CMOs in the xbarNikos Nikoleris
2017-12-05mem: Add support for handling CMOs in the MSHRsNikos Nikoleris
2017-12-05mem: Add support for CMOs in the cacheNikos Nikoleris
2017-12-05mem: Promote deferred targets only when the block is validNikos Nikoleris
2017-12-05mem: Add support for cache maintenance operation requestsNikos Nikoleris
2017-12-05mem: Support for specifying the destination of a WriteCleanNikos Nikoleris
2017-12-05mem: Add support for WriteClean packets in the memory systemNikos Nikoleris
2017-12-05mem: Add a WriteClean command to the packet classNikos Nikoleris
2017-12-05mem-cache: Add support for checking whether a cache is busyNikos Nikoleris
2017-12-05mem: Add function to check if the slave can receive a timing reqNikos Nikoleris
2017-12-05mem: Add the notion of point of unification in the coherent xbarNikos Nikoleris
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
2017-12-05learning_gem5: Add code for simple SimObjectJason Lowe-Power
2017-12-04base: Rework the trie dump function to accept a different ostream.Gabe Black
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-12-04misc: Move the ExitLogger class definition into misc.ccGabe Black
2017-12-04tests: Remove trietest's dependence on cprintf.Gabe Black
2017-12-04tests: Add a ptr helper function trietest.Gabe Black
2017-12-04tests: Get rid of the bitvectest unit test.Gabe Black
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
2017-11-29cpu: Don't override ISA if provided by userAndreas Sandberg
2017-11-29cpu-minor: Add missing instruction statsDavid Guillen Fandos
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
2017-11-28arch-arm: Add haveEL pseudocode functionGiacomo Travaglini
2017-11-28arch-arm: Add assertions when extracting an ArmSystem from a TCGiacomo Travaglini