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2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
and schedules the event immediately. --HG-- extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
--HG-- extra : convert_revision : 36c33d25a3b23ac2094577aa504c24fac0f3ffcc
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
port. It would be better to move this to python IMO but for now I'll stick in a compatibility hack. --HG-- extra : convert_revision : a81a29cbd43becd0e485559eb7b2a31f7a0b082d
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-15Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 32dc1bec7fdb1ecb8879ed2dd745c4b23929aeab
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 8a501917daf81021212d136b4ebbfa059b452a13
2007-05-14Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : e445097240af7b4e73efaca855cd1f217cf00313
2007-05-14couple more bug fixes for intel nicAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes --HG-- extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
2007-05-14add uglyiness to fix dmasAli Saidi
src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself --HG-- extra : convert_revision : 1df52ab61d7967e14cc377c560495430a6af266a
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
Compiles but not tested. --HG-- extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9
2007-05-13fix handling of atomic packetsAli Saidi
fix up code for counting requests and responses --HG-- extra : convert_revision : 0d70981ee41c5d9c36cad01bd505281a096f6119
2007-05-11Move full CPU sim object stuff into the encumbered directoryNathan Binkert
--HG-- extra : convert_revision : 788068dd4f4994d0016dba7e8705359d45a3a45c
2007-05-11Float should have a c++ param typeNathan Binkert
--HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673
2007-05-11total should be the sum of the vector result of an operation,Nathan Binkert
not sum the operands and then apply the operation. --HG-- extra : convert_revision : 06486e59b3dd9588b458ef45c341cc4f2554dc09
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-10Merge zizzer:/bk/newmemAli Saidi
into pb15.local:/Users/ali/work/m5.newmem.zeep tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: the new version of this is what we want --HG-- extra : convert_revision : 204df6f8181df81e423def4695cd81544c485c47
2007-05-10add/update parameters for bus bridgeAli Saidi
--HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91
2007-05-09couple of updates in the intel nicAli Saidi
--HG-- extra : convert_revision : da68e5e6411000d9d5247f769ee528a443286c61
2007-05-09update for new reschedule semanticsAli Saidi
--HG-- extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still ↵Ali Saidi
constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list --HG-- extra : convert_revision : 3595ad932015a4ce2bb72772da7850ad91bd09b1
2007-05-09fix the translating ports so it can add a page on a faultAli Saidi
--HG-- extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
2007-05-09Merge zizzer:/bk/newmemAli Saidi
into udhcp-macvpn-703.public.engin.umich.edu:/Users/ali/work/m5.newmem --HG-- extra : convert_revision : e977c5b194954774b6503484797f1c1e0eb4e425
2007-05-09bit_val was being used directly in the statement in return. If type B had ↵Ali Saidi
fewer bits than last, bit_val << last would get the wrong answer. src/base/bitfield.hh: bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. --HG-- extra : convert_revision : cbc43ccd139f82ebbd65f30af5d05b87c4edac64
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ↵Ali Saidi
it always returns true and nacks the packet if there isn't sufficient buffer space fix the timing cpu to handle receiving a nacked packet src/cpu/simple/timing.cc: make the timing cpu handle receiving a nacked packet src/mem/bridge.cc: src/mem/bridge.hh: the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space --HG-- extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
2007-05-07fix partial writes with a functional memory hackAli Saidi
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-01change the way dprintf works so the cache accesses required to fulfill the ↵Ali Saidi
dprintf aren't show in between the Cycle: name: printing and the actual formatted string being printed --HG-- extra : convert_revision : 8876ba938ba971f854bab490c9af10db039a2e83
2007-05-01fix flushAddr so it doesn't modify an iterator that has been deletedAli Saidi
--HG-- extra : convert_revision : 8b7e4948974517b13616ab782aa7e84471b24f10
2007-05-01Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 7e4b82f5949c0807d93fff80c44a8828968d1248
2007-05-01initialize lastTxInt to 0Ali Saidi
--HG-- extra : convert_revision : 4c5e9c2145b12fdeba91f3fdd8963c35abe326c2
2007-04-30always skip the debugprintf function (DebugPrintf traceflag shouldn't ↵Ali Saidi
matter). Otherwise, when you turn on debugprintf alters the execution --HG-- extra : convert_revision : 1c9a665e3b7234cacf06c31d2e7886244a9e82bc
2007-04-30fix igbe bugAli Saidi
--HG-- extra : convert_revision : 01ffc08f5c1ec827a42f60562ae7e10176ffdb7f
2007-04-30fix console printing bugAli Saidi
--HG-- extra : convert_revision : 5481b72b22e7a2cf3367d777309bc30201f3b1fc
2007-04-30add the ability for the ethernet device to check if the link is busyAli Saidi
--HG-- extra : convert_revision : 0dc0c4c4546869261f4508ad22a6a85aecf3c334
2007-04-27gcc 4.1 claims that mem_data might be used uninitialized,Nathan Binkert
though I don't believe that's true. Placate it anyway. --HG-- extra : convert_revision : dcd9427af14f0e7a33510054bee4ecbe73e050be
2007-04-26Remove extra delete that was causing segfault.Kevin Lim
--HG-- extra : convert_revision : 8a27ed80308c95988f3bc43d670dc0ac9e946d39
2007-04-26Remove unnecessary check.Kevin Lim
--HG-- extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
2007-04-23Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab
2007-04-22Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
2007-04-22Use proper cycles for IPC and CPI equations.Kevin Lim
src/cpu/o3/cpu.cc: Use proper cycles for these equations. --HG-- extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae
2007-04-21fixes for solaris compileAli Saidi
--HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and ↵Ali Saidi
not a cpp file because c99 (which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment. src/arch/alpha/isa/fp.isa: src/arch/sparc/isa/formats/basic.isa: use m5_fesetround()/m5_fegetround() istead of fenv interface directly src/arch/sparc/isa/includes.isa: use base/fenv instead of fenv directly src/base/SConscript: add fenv to sconscript src/base/fenv.hh: src/base/random.cc: m5 implementation to standerdize fenv across platforms. --HG-- extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c
2007-04-18Move the turbolaser python simobject stuff into theNathan Binkert
encumbered directory --HG-- extra : convert_revision : 7062ce81183b989f0d922b00d02433633474a854
2007-04-18fix SIGUSR1 and SIGUSR2 by clearing the variables afterNathan Binkert
they're used --HG-- extra : convert_revision : ed5351f291d45d585bf811a062e162e16b86e886
2007-04-16Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 8630b3771678b68d5cd12a61f7a4de2e3443a8d7
2007-04-16Fixes for splash, may conflict with Korey's SMT work and doesn't support ↵Ron Dreslinski
03cpu yet. src/cpu/simple/base.cc: Cpu's should start as unallocated, not suspended src/cpu/simple_thread.cc: Wait for a thread to be assigned to activate the cpu src/kern/tru64/tru64.hh: When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one. --HG-- extra : convert_revision : 5e3ad2e96b4a715ed38293ceaccff5b9f4ea7985
2007-04-12Completely re-work how the scons framework incorporates swigNathan Binkert
and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. --HG-- extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 16:53:52 +0000