gem5 - gem5

Age	Commit message (Expand)	Author
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-04-23	arm: Correctly display disassembly of vldmia/vstmia	Curtis Dunham
2014-04-23	sim: Use correct unit for abort message	Andreas Hansson
2014-04-23	cpu: Fix setTranslateLatency() bug for squashed instructions	Mitchell Hayenga
2014-04-23	misc: Proper type check and import for PortRef	Sascha Bischoff
2014-04-01	cpu: Fix case where o3 lsq could print out uninitialized data	Mitch Hayenga
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-04-23	arm: Don't use a stack allocated mnemonic	Mitchell Hayenga
2014-04-23	cpu: Add O3 CPU width checks	Dam Sunwoo
2014-04-23	base: explicitly suggest potential use of 'All' debug flags	Curtis Dunham
2014-04-23	arch: remove 'null update' check in isa-parser	Curtis Dunham
2014-02-10	stats: better error message for uninitialized statistic	Curtis Dunham
2014-04-19	ruby: slicc: remove old documentation	Nilay Vaish
2014-04-19	ruby: slicc: slight change to rule for transitions	Nilay Vaish
2014-04-19	o3: Fix occupancy checks for SMT	Faissal Sleiman
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-04-09	kvm, x86: Add initial support for multicore simulation	Andreas Sandberg
2014-04-09	dev: Protect PollEvent processing when running in parallel mode	Andreas Sandberg
2014-04-08	ruby: slicc: change enqueue statement	Nilay Vaish
2014-04-08	ruby: coherence protocols: drop the phrase IntraChip	Nilay Vaish
2014-04-03	sim: Add the ability to lock and migrate between event queues	Andreas Sandberg
2014-03-25	cpu: o3: lsq: Fix TSO implementation	Marco Elver
2014-03-23	mem: Track DRAM read/write switching and add hysteresis	Andreas Hansson
2014-03-23	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	Andreas Hansson
2014-03-23	mem: Change memory defaults to be more representative	Andreas Hansson
2014-03-23	mem: Add close adaptive paging policy to DRAM controller model	Wendy Elsasser
2014-03-23	mem: DRAM controller tidying up	Andreas Hansson
2014-03-23	mem: Fix bug in DRAM bytes per activate	Andreas Hansson
2014-03-23	mem: Limit the accesses to a page before forcing a precharge	Andreas Hansson
2014-03-23	mem: Make DRAM write queue draining more aggressive	Andreas Hansson
2014-03-23	cpu: DRAM Traffic Generator	Neha Agarwal
2014-03-23	mem: DDR3 config for comparing with DRAMSim2	Neha Agarwal
2014-03-23	mem: More descriptive address-mapping scheme names	Andreas Hansson
2014-03-23	misc: Fix -q (quiet) flag	Stan Czerniawski
2014-03-23	ruby: Move Ruby debug flags to ruby dir and remove stale options	Andreas Hansson
2014-03-23	mem: Include the DRAMSim2 wrapper in NULL build	Andreas Hansson
2014-03-23	mem: CommMonitor trace warn on non-timing mode	Sascha Bischoff
2014-03-23	cpu: Add basic check to TrafficGen initial state	Stan Czerniawski
2014-03-23	dev: Fix IsaFake's cxx_header setting	Andrew Bardsley
2014-03-23	arm: m5ops readfile64 args broken, offset coming through garbage	Eric Van Hensbergen
2014-03-23	base: Fix error message time unit (cycle -> tick)	Andreas Hansson
2014-03-20	ruby: consumer: avoid accessing wakeup times when waking up	Nilay Vaish
2014-03-20	ruby: garnet: convert network interfaces into clocked objects	Nilay Vaish
2014-03-20	ruby: slicc: code refactor	Nilay Vaish
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-03-16	kvm: Clean up signal handling	Andreas Sandberg
2014-03-16	kvm: x86: Adjust PC to remove the CS segment base address	Andreas Sandberg
2014-03-16	kvm: x86: Add support for x86 INIT and STARTUP handling	Andreas Sandberg
2014-03-12	alpha: Small removal of dead comments/code from alpha ISA	Paul Rosenfeld