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Age
Commit message (
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Author
2010-12-08
ruby: remove Ruby asserts for m5.fast
Brad Beckmann
2010-12-08
MIPS: Take advantage of new PCState syntax.
Gabe Black
2010-12-08
POWER: Take advantage of new PCState syntax.
Gabe Black
2010-12-08
SPARC: Take advantage of new PCState syntax.
Gabe Black
2010-12-08
X86: Take advantage of new PCState syntax.
Gabe Black
2010-12-07
ISA: Get the parser to support pc state components more elegantly.
Gabe Black
2010-12-07
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
Ali Saidi
2010-12-07
O3: Support squashing all state after special instruction
Ali Saidi
2010-12-07
O3: Make all instructions that write a misc. register not perform the write u...
Giacomo Gabrielli
2010-12-07
O3: Support SWAP and predicated loads/store in ARM.
Min Kyu Jeong
2010-12-07
ARM: Support switchover with hardware table walkers
Ali Saidi
2010-12-01
ruby: Converted old ruby debug calls to M5 debug calls
Nilay Vaish
2010-11-26
IGbE: return 0 on an invalid descriptor size instead of -1.
Ali Saidi
2010-11-23
Copyright: Add AMD copyright to the param changes I just made.
Gabe Black
2010-11-23
Params: Add parameter types for IP addresses in various forms.
Gabe Black
2010-11-23
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Gabe Black
2010-11-23
X86: Obey the PCD (cache disable) bit in the page tables.
Gabe Black
2010-11-22
X86: Mark IO space accesses as uncachable.
Gabe Black
2010-11-22
IDE,X86: Fix IDE controller BAR configuration for x86.
Gabe Black
2010-11-20
random: small comment about our random number generator and its origin
Nathan Binkert
2010-11-19
SE: Fix simulating more than 4GB of RAM in SE mode
Ali Saidi
2010-11-19
SCons: Support building without an ISA
Ali Saidi
2010-11-18
O3: Fix fp destination register flattening, and index offset adjusting.
Gabe Black
2010-11-15
O3: Make O3 support variably lengthed instructions.
Gabe Black
2010-11-15
O3: reset architetural state by calling clear()
Ali Saidi
2010-11-15
ARM: Add comment about the organization of the IT state register
Ali Saidi
2010-11-15
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Giacomo Gabrielli
2010-11-15
O3: prevent a squash when completeAcc() modifies misc reg through TC.
Min Kyu Jeong
2010-11-15
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...
Ali Saidi
2010-11-15
SCons: Cleanup SCons output during compile
Ali Saidi
2010-11-15
ARM: Add a Keyboard Mouse Interface controller
William Wang
2010-11-15
ARM: Implement a CLCD Frame buffer
William Wang
2010-11-15
ARM: Add support for GDB on ARM
William Wang
2010-11-15
ARM: Make utility.hh meet style guidelines
Ali Saidi
2010-11-15
ARM: Add support for a dumb IDE controller
Ali Saidi
2010-11-15
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
Ali Saidi
2010-11-15
ARM: Add support for switching CPUs
Ali Saidi
2010-11-15
ARM: Use the correct delete operator for RFE
Ali Saidi
2010-11-15
ARM: Fix SRS instruction to micro-code memory operation and register update.
Ali Saidi
2010-11-15
CPU: Fix bug when a split transaction is issued to a faster cache
Ali Saidi
2010-11-15
ARM: Do something predictable for an UNPREDICTABLE branch.
Ali Saidi
2010-11-11
Params: Fix an off by one error and a misleading comment.
Gabe Black
2010-11-11
SimObject: Add a comment near clear_child that it's unlikely to be called.
Gabe Black
2010-11-11
SPARC: Clean up some historical style issues.
Gabe Black
2010-11-09
SimObject: Use "self" when calling the clear_child method.
Gabe Black
2010-11-08
X86: Fix X86_FS compilation.
Gabe Black
2010-11-08
ARM: Add some TLB statistics for ARM
Ali Saidi
2010-11-08
ARM: Add checkpointing support
Ali Saidi
2010-11-08
ARM: Add support for M5 ops in the ARM ISA
Ali Saidi
2010-11-08
ARM: Keep the warnings to a minimum.
Ali Saidi
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