summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-04-13x86: implements x87 mult/div instructionsNilay Vaish
2015-04-13ruby: allow restoring from checkpoint when using DRAMCtrlLena Olson
2015-04-13sim: Use NULL instead of None for testing filenames.Nilay Vaish
2015-04-13sim: fix function for emulating dup()Nilay Vaish
2015-04-08config: Support full-system with SST's memory systemCurtis Dunham
2015-04-03dev: (un)serialize fix for the RTC and RTC Timer Interrupt eventsNikos Nikoleris
2015-04-03sim: correct check for endianessRuslan Bukin
2015-04-03dev: Extend access width for IDE control registersRuslan Bukin
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-04-03x86: fix debug trace output for mwaitLena Olson
2015-03-27mem: Support any number of master-IDs in stride prefetcherStephan Diestelhorst
2015-03-27mem: Allocate cache writebacks before new MSHRsAndreas Hansson
2015-03-27mem: Cleanup flow for uncacheable accessesAndreas Hansson
2015-03-27mem: Ignore uncacheable MSHRs when finding matchesAndreas Hansson
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
2015-03-27mem: Modernise MSHR iterators to C++11Andreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
2015-03-27mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHEDAli Jafri
2015-03-26sim: Update limit_event reuse to final versionCurtis Dunham
2015-03-26cpu: Fix InstPBTrace inheritanceAndreas Hansson
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-03-23misc: quote args in echoed command lineSteve Reinhardt
2015-03-23sim: Reuse the same limit_event in simulate()Curtis Dunham
2015-03-23mem: Tidy up RequestAndreas Hansson
2015-03-19arm: Add a GICv2m deviceMatt Evans
2015-03-19arm: Remove the 'magic MSI register' in the GIC (PL390)Matt Evans
2015-03-19cpu: Fix TrafficGen message formatWendy Elsasser
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2015-03-19mem: Enable CommMonitor to output traces in atomic modeGeoffrey Blake
2015-02-11mem: remove redundant test in in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: add local var in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-14mem: clean up write buffer check in Cache::handleSnoop()Steve Reinhardt
2015-03-09cpu: o3: another assert instead of checkNilay Vaish
2015-03-09cpu: o3: Remove unused code in iew, add assert instead.Nilay Vaish
2015-03-09cpu: o3: commit: mark pipeline delay variable as constsNilay Vaish
2015-03-09cpu: o3: remove unused stat variables.Nilay Vaish
2015-03-09cpu: o3: combine if with same conditionNilay Vaish
2015-03-09cpu: o3: remove member variable squashCounterNilay Vaish
2015-03-09cpu: o3: remove unused function annotateMemoryUnits()Nilay Vaish
2015-03-02mem: Unify all cache DPRINTF address formattingAndreas Hansson
2015-03-02mem: Fix cache MSHR conflict determinationAndreas Hansson
2015-03-02mem: Add byte mask to Packet::checkFunctionalAndreas Hansson
2015-03-02mem: Add option to force in-order insertion in PacketQueueStephan Diestelhorst
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02mem: Add crossbar latenciesMarco Balboni
2015-03-02dev, arm: Clean up PL011 and rewrite interrupt handlingAndreas Sandberg
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 09:32:34 +0000