Age | Commit message (Collapse) | Author |
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Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
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check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
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--HG--
extra : convert_revision : f7d21fc277dd7172c244d83fb012883dc8b67895
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simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc:
make AsiIsLittle() be all the little asis.
Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
clean up the do*Fault code.... Make it work like legion, in particular
pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
implement some more twin ASIs
src/arch/sparc/tlb.cc:
All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
softint is supported now, no more need to
--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
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--HG--
extra : convert_revision : 4f5c7f9c7653e1e9ebbd488c07426d9f944bb25f
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
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Only implemented for ELf. Someone might want to implement it for ecoff and some point
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add a function to check if an executable is dynamic
src/sim/process.cc:
check if an executable is dynamic and die if it is
--HG--
extra : convert_revision : 830b1b50b08a5abaf895ce6251bbc702c986eebf
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Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)
--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
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--HG--
extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
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--HG--
extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
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(the bit positition that is set in softint)
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extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
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--HG--
extra : convert_revision : 77bfdf07a49d41a2392f429fdc632c1461ac504c
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--HG--
extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1
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Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0
--HG--
extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
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--HG--
extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
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src/arch/sparc/interrupts.hh:
condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
implement HINTP
src/arch/sparc/ua2005.cc:
don't post interrupt unless it is enabled.
--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
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--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
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could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry
--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
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--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
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instruction set curMacroStaticInst to null
This way we'll jump immediately to the handler
--HG--
extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e
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much meaningless with all the copying that goes on
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extra : convert_revision : 4d2c1bb72c0344d78d9c3d5958feb3de247102a0
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instruction (because of a fault on the first op) we don't lose sync with legion
Only print TLB if there is a tlb difference
--HG--
extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d
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--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
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Increment instruction count on first micro-op instead of last
src/arch/sparc/isa/decoder.isa:
Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
Add IsFirstMicroop flag to static insts
--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge between ali and me.
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extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
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formatting/indentation for case statements
src/arch/sparc/ua2005.cc:
formatting/indentation for case statements
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extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
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i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
src/arch/sparc/ua2005.cc:
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
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forgot to remove last time.
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extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
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src/arch/sparc/intregfile.cc:
some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
legion always returns du and dl set, so we need to emulate that for now at least
--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
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fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis
src/arch/sparc/miscregfile.cc:
get rid of some warnings
fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
make warning less verbose
--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
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configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
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small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile
src/arch/alpha/interrupts.hh:
small fix for alpha compile
src/arch/alpha/pagetable.hh:
small fix so ALPHA_FS will build on macs
--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
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CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
fill in how we do interrupts on sparc a little bit.
1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
2) fill in getInterrupts() a little bit.
also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
1) update formatting
2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.
--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
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PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
1) s/Resumeable/Resumable/gc
2) s/if(/if (/gc
3) keep variables lowercase
4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
add bitfield masks for some important ASRs (HPSTATE, PSTATE).
--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
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two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.
--HG--
extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
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to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
fix softint and fprs in miscregfile
--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
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there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.cc:
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
correct protection defines
src/arch/sparc/ua2005.cc:
set the softint appropriately on an timer compare interrupt
--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e8ac13e1222796ab362fabb9b19694682538da29
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appropriate time
turn warnings into dprintfs
src/arch/sparc/miscregfile.cc:
turn dprintfn into dprintfs
--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
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tell if the script is run from m5 as the m5 script
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extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
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--HG--
extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949
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formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
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src/cpu/o3/commit_impl.hh:
Oops, changed the logic a little bit. Fix it up to how it used to be.
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extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
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into iceaxe.:/Volumes/work/m5/incoming
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extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
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--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
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Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
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Only print faults instructions that aren't traps or faulting loads
src/cpu/exetrace.cc:
Compare the legion and m5 tlbs and printout any differences
Only show differences if the instruction isn't a trap and isn't a memory
operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
update the m5<->legion interface to add tlb data
--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
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--HG--
extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
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