gem5 - gem5

Age	Commit message (Expand)	Author
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-10-15	Clock: Inherit the clock from parent by default	Andreas Hansson
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-11	Doxygen: Update the version of the Doxyfile	Andreas Hansson
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-10-02	ruby: rename template_hack to template	Nilay Vaish
2012-10-02	ruby: remove unused code in protocols	Nilay Vaish
2012-10-02	ruby: remove some unused things in slicc	Nilay Vaish
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-30	MI coherence protocol: add copyright notice	Nilay Vaish
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-25	Statistics: Add a function to configure periodic stats dumping	Sascha Bischoff
2012-09-25	ARM: added support for flattened device tree blobs	Dam Sunwoo
2012-09-25	O3: Pack the comm structures a bit better to reduce their size.	Ali Saidi
2012-09-25	mem: Add a gasket that allows memory ranges to be re-mapped.	Ali Saidi
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	arm: Use a static_assert to test that miscRegName[] is complete	Andreas Sandberg
2012-09-25	base: Check for static_assert support and provide fallback	Andreas Sandberg
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	sim: Remove SimObject::setMemoryMode	Andreas Sandberg
2012-09-25	CPU: Add abandoned instructions to O3 Pipe Viewer	Djordje Kovacevic
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-09-25	build: Add missing dependencies when building param SWIG interfaces	Andreas Sandberg
2012-09-23	RubyPort and Sequencer: Fix draining	Joel Hestness
2012-09-21	DRAM: Introduce SimpleDRAM to capture a high-level controller	Andreas Hansson
2012-09-21	TrafficGen: Add a basic traffic generator	Andreas Hansson
2012-09-21	Mem: Tidy up bus member variables types	Andreas Hansson
2012-09-21	SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex	Lluc Alvarez
2012-09-20	bus: removed outdated warn regarding 64 B block sizes	Anthony Gutierrez
2012-09-19	Mem: Remove the file parameter from AbstractMemory	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-19	AddrRange: Simplify Range by removing stream input/output	Andreas Hansson
2012-09-19	AddrRange: Remove unused range_multimap	Andreas Hansson
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-09-18	ruby: eliminate typedef integer_t	Nilay Vaish
2012-09-18	ruby: avoid using g_system_ptr for event scheduling	Nilay Vaish
2012-09-18	Mem: Add a maximum bandwidth to SimpleMemory	Andreas Hansson
2012-09-14	gcc: Enable Link-Time Optimization for gcc >= 4.6	Andreas Hansson
2012-09-14	scons: Add a target for google-perftools profiling	Andreas Hansson
2012-09-14	scons: Restructure ccflags and ldflags	Andreas Hansson
2012-09-14	scons: Use c++0x with gcc >= 4.4 instead of 4.6	Andreas Hansson
2012-09-12	Standard Switch: Drain the system before switching CPUs	Joel Hestness
2012-09-12	Base CPU: Initialize profileEvent to NULL	Joel Hestness
2012-09-12	Ruby: Modify Scons so that we can put .sm files in extras	Jason Power