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AgeCommit message (Expand)Author
2015-12-18sim: Use the old work item behavior by defaultAndreas Sandberg
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
2015-12-14sim: Add an option to forward work items to PythonAndreas Sandberg
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-12-10dev: Add missing SConscript in src/dev/i2cAndreas Sandberg
2015-12-10dev: Move storage devices to src/dev/storage/Andreas Sandberg
2015-12-10dev: Move network devices to src/dev/net/Andreas Sandberg
2015-12-10dev: Move i2c functionality to src/dev/i2c/Andreas Sandberg
2015-12-10dev: Move the CopyEngine class to src/dev/pciAndreas Sandberg
2015-12-10dev: Move existing PCI device functionality to src/dev/pciAndreas Sandberg
2015-11-05sim: Disable gzip compression for writefile pseudo instructionSascha Bischoff
2015-09-18dev, arm: Add gem5 extensions to support more than 8 coresKarthik Sangaiah
2015-12-09mem: remove acq/rel cmds from packet and add mem fence reqTony Gutierrez
2015-12-09syscall_emul: don't check host fd when allocating target fdSteve Reinhardt
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
2015-12-07cpu: Create record type enum for elastic tracesRadhika Jagtap
2015-12-07cpu: Add TraceCPU to playback elastic tracesRadhika Jagtap
2015-12-07mem: Add instruction sequence number to requestRadhika Jagtap
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
2015-12-04sim: Get rid of the non-const serialize() methodAndreas Sandberg
2015-12-04arm, config: Automatically discover available platformsAndreas Sandberg
2015-12-04dev, arm: Disable R/B swap in HDLCD by defaultAndreas Sandberg
2015-12-04dev, arm: Split MCC and DCC subsystemsAndreas Sandberg
2015-12-04sim: Add support for generating back traces on errorsAndreas Sandberg
2015-12-03arm: Add support for automatic boot loader selectionAndreas Sandberg
2015-12-03dev, mips: Remove the unused MaltaPChip classAndreas Sandberg
2015-12-01config: Fix broken SimObject listingAndreas Sandberg
2015-11-24dev: Remove unnecessary header includeAndreas Sandberg
2015-11-25mem: Fix search-replace issues in DRAMPower wrapper licenseAndreas Hansson
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
2015-11-22arm, dev: Fix flash model serialization code typosGeoffrey Blake
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
2015-11-22arm: Fix fplib 128-bit shift operatorsNathanael Premillieu
2015-11-22cpu: Fix memory leak in traffic generatorAndreas Hansson
2015-11-20cpu: Enforce 1 interrupt controller per threadAndreas Sandberg
2015-11-16Merged changesets: 47e2adf7fb1a and b65d4e878ed2Nilay Vaish
2015-11-16x86: Invalidating TLB entry on page faultSwapnil Haria
2015-11-16x86: cpuid: add family to warn() messageBjoern A. Zeeb
2015-11-16x86: pagetable walker: fix typo in commentBjoern A. Zeeb
2015-11-16sparc: Make remote debugging with gdb workPalle Lyckegaard
2015-11-16o3: drop unused statistic wbPenalized and wbPenalizedRateNilay Vaish
2015-11-15arm: Add missing explicit overrides for classic cachesAndreas Sandberg
2015-07-20ruby: added stl vector of ints to be used by SLICCBrad Beckmann
2015-11-13slicc: fixes for the Address to Addr changeset (11025)Tony Gutierrez
2015-11-13ruby: add BoolVecJoe Gross
2015-07-20mem: add boolean to disable PacketQueue's size sanity checkBrad Beckmann
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