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2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: remove redudant check whether the cache forwards snoopsNikos Nikoleris
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: change NULL to nullptr in the cache related classesNikos Nikoleris
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-19config, x86: Properly space pad the X86IntelMPBus Entry descriptionsBjoern A. Zeeb
According to the Intel Multi Processor Specification rev 1.4 (-006) (*), section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII (blank-filled) strings<<. This patch properly pads the entries with the missing spaces at the end. (*) http://www.intel.com/design/pentium/datashts/24201606.pdf Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19arm,dev: PL011 UART_FR read status enhancementBjoern A. Zeeb
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19x86, dev: properly space the APIC registersBjoern A. Zeeb
Registers are 0x10 and not 0x8 apart. The latter leads to invalid calculations of index in array which in turn means that we will not find the interrupt we were looking (been notified) for in the OS. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19dev, virtio: properly set PCI address space to use IOREGBjoern A. Zeeb
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped. Set the correct bit on the PCI address accordingly. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-16gpu-compute: fix bug in GPUDynInst::isScalarRegister()Tony Gutierrez
2016-05-06gpu-compute: fix spacing in GPUDynInst ctorTony Gutierrez
2016-05-06gpu-compute: fix uninitialized member bug in GPUDynInstTony Gutierrez
the n_reg field in the GPUDynInst is not currently set in the constructor. if it is not set externally, there are assertion failures that may occur if the random value it gets is just right. here we set it to 0 by default.
2016-05-06dev, arm: Update GIC to use GICv2 register namingAndreas Sandberg
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-04-27arm: Remove BreakPCEvent on guest kernel panicAndreas Sandberg
The LinuxArmSystem class normally provides support for panicing gem5 if the simulated kernel panics. When this is turned off (default), gem5 uses a BreakPCEvent to provide a debugger hook into the simulator when the kernel crashes. This hook unconditionally kills gem5 with a SIGTRAP unless gem5 is compiled in fast mode. This is undesirable since the panic_on_panic param already provides similar functionality. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Make GIC interrupt lines configurableAndreas Sandberg
Add support for overriding the number of interrupt lines in the ARM KvmGic. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27kvm, arm: Refactor KVM GIC deviceAndreas Sandberg
Factor out the kernel device wrapper from the KvmGIC and put it in a separate class. This will simplify a future kernel/gem5 hybrid GIC. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27dev: Fix incorrect terminal backlog handlingAndreas Sandberg
The Terminal device currently uses the peek functionality in gem5's circular buffer implementation to send existing buffered content on the terminal when a new client attaches. This functionallity is however not implemented correctly and re-sends the same block multiple time. Add the required functionality to peek with an offset into the circular buffer and change the Terminal::accept() implementation to send the buffered contents. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-26ruby: Rename pkt to m_pkt so it may be accessed via SLICCMatthew Poremba
Allow usage of packet class in ruby for convenience purposes. This may be used to access members of the packet/request class (e.g., via helper functions) and/or push protocol specific information to the packets SenderState without needing to modify SLICC types and protocols in multiple locations.
2016-04-21mem: Include WriteLineReq in cache demand statsAndreas Hansson
Somehow the WriteLineReq were never added to the list of commands considered demand.
2016-04-21mem: Remove unused cache statsAndreas Hansson
Prune cache stats that are never actually used.
2016-04-21mem: Deallocate all write-queue entries when sentAndreas Hansson
This patch removes the write-queue entry tracking previously used for uncacheable writes. The write-queue entry is now deallocated as soon as the packet is sent. As a result we also forego the stats for uncacheable writes. Additionally, there is no longer a need to attach the write-queue entry to the packet.
2016-04-21mem: Align downstream cache packet creation in atomic and timingAndreas Hansson
This patch makes the control flow more uniform in atomic and timing, ultimately making the code easier to understand.
2016-04-15ruby: Fix block_on behaviorJoel Hestness
Ruby's controller block_on behavior aimed to block MessageBuffer requests into SLICC controllers when a Locked_RMW was in flight. Unfortunately, this functionality only partially works: When non-Locked_RMW memory accesses are issued to the sequencer to an address with an in-flight Locked_RMW, the sequencer may pass those accesses through to the controller. At the controller, a number of incorrect activities can occur depending on the protocol. In MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2 transfer, which cannot be serviced, because the block_on functionality blocks the trigger queue, resulting in a deadlock. Further, if an intermediate store arrives (e.g. from a separate SMT thread), the sequencer allows the request through to the controller, and the atomicity of the Locked_RMW may be broken. To avoid these problems, disallow the Sequencer from passing any memory accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in- flight.
2016-04-15arm,dev: remove PMU assertion hit on resetBjoern A. Zeeb
Remve the assertion that we always need to add a delta larger than zero as that does not seem to be true when we hit it in the 'PMU reset cycle counter to zero' case. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15mem: FreeBSD does not provide MAP_NORESERVE eitherBjoern A. Zeeb
Like OS X, FreeBSD does not support MAP_NORESERVE. Handle accordingly and update comment. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
A few warnings (and thus errors) pop up after being added to -Wall: 1. -Wmisleading-indentation In the auto-generated code there were instances of if/else blocks that were not indented to gcc's liking. This is addressed by adding braces. 2. -Wshift-negative-value gcc is clever enougn to consider ~0 a negative constant, and rightfully complains. This is addressed by using mask() which explicitly casts to unsigned before shifting. That is all. Porting done.
2016-04-12misc: Appease clang...againAndreas Hansson
Once again, clang is having issues with recently committed code. Unfortunately HSAIL_X86 is still broken.
2016-04-07mem: Add priority to QueuedPrefetcherRekai Gonzalez Alberquilla
Queued prefetcher entries now count with a priority field. The idea is to add packets ordered by priority and then by age. For the existing algorithms in which priority doesn't make sense, it is set to 0 for all deferred packets in the queue.
2016-04-07mem: Handful extra features for BasePrefetcherRekai Gonzalez Alberquilla
Some common functionality added to the base prefetcher, mainly dealing with extracting the block address, page address, block index inside the page and some other information that can be inferred from the block address. This is used for some prefetching algorithms, and having the methods in the base, as well as the block size and other information is the sensible way.
2016-04-07mem: Add Program Counter to MemTraceProbeVictor Garcia
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
Added stat to the cache to account for HardPF'ed blocks that are evicted before being referenced (over-prefetching).
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-04-05cpu: Implement per-thread GHRsMitch Hayenga
Branch predictors that use GHRs should index them on a per-thread basis. This makes that so. This is a re-spin of fb51231 after the revert (bd1c6789).
2016-04-05cpu: Add an indirect branch target predictorMitch Hayenga
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209 This is a re-spin of fb9d142 after the revert (bd1c6789).
2016-04-05cpu: Fix BTB threading oversightMitch Hayenga
The extant BTB code doesn't hash on the thread id but does check the thread id for 'btb hits'. This results in 1-thread of a multi-threaded workload taking a BTB entry, and all other threads missing for the same branch missing.
2016-04-06misc: Bail out of DVFS dot if we cannot resolve the domainsSascha Bischoff
This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes. Minor fixup for 0aeca8f.
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
2016-04-05cpu: Implement per-thread GHRsCurtis Dunham
Branch predictors that use GHRs should index them on a per-thread basis. This makes that so.
2016-04-05cpu: Add an indirect branch target predictorMitch Hayenga
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209
2016-04-05cpu: Fix BTB threading oversightMitch Hayenga
The extant BTB code doesn't hash on the thread id but does check the thread id for 'btb hits'. This results in 1-thread of a multi-threaded workload taking a BTB entry, and all other threads missing for the same branch missing.
2016-04-05power: Add support for power modelsDavid Guillen Fandos
This patch adds some basic support for power models in gem5. The power interface is defined so it can interact with thermal models as well. It implements a simple power evaluator that can be used for simple power models that express power in the form of a math expression. These expressions can use stats within the same SimObject (or down its hierarchy) and some magic variables such as "temp" for temperature. In future patches we will extend this functionality to allow slightly more complex expressions. The model allows it to be extended to use other kinds of models. Finally, the thermal model is updated to use the power usage as input.
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
Add functionality to the BaseCPU that will put the entire CPU into a low-power idle state whenever all threads in it are idle.
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats.
2015-05-13sim: Thermal support for LinuxDavid Guillen Fandos
This patch enables Linux to read the temperature using hwmon infrastructure. In order to use this in your gem5 you need to compile the kernel using the following configs: CONFIG_HWMON=y CONFIG_SENSORS_VEXPRESS=y And a proper dts file (containing an entry such as): dcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; temp@0 { compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; };
2015-05-12sim: Adding thermal model supportDavid Guillen Fandos
This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch.
2016-04-05cpu: Add instruction opclass histogram to minorMitch Hayenga
2015-12-15misc: Add secondary dot output for DVFS domainsSascha Bischoff
This patch adds a secondary dot output file which shows the DVFS domains. This has been done separately for now to avoid cluttering the already existing diagram. Due to the way that the clock domains are assigned to components in gem5, this output must be generated after the C++ objects have been instantiated. This further motivates the need to generate this file separately to the current dot output, and not to replace it entirely.
2015-12-11sim: Add additional debug information when drainingSascha Bischoff
This patch adds some additional information when draining the system which allows the user to debug which SimObject(s) in the system is failing to drain. Only enabled for the builds with tracing enabled and is subject to the Drain debug flag being set at runtime.
2016-04-01sim: Fix clock_domain unserializationSascha Bischoff
This patch addresses an issue with the unserialization of clock domains. Previously, the previous performance level was not restored due to a bug in the code, which detected the post-unserialize update as superfluous. This patch splits the setting of the clock domain into two parts. The original interface of perfLevel is retained, but the actual update takes place in signalPerfLevelUpdate, which is private to the class. The perfLevel method checks that if the new performance level is different to the previous performance level, and will only call signalPerfLevelUpdate if there is a change. Therefore, the performance level is only updated, and voltage domains notified, if there is an actual change. The split functionality allows signalPerfLevelUpdate to be called by startup() to explicitly force an update post unserialization.