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AgeCommit message (Expand)Author
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
2013-02-15ARM: Fix an issue with clang generating wrong code.Ali Saidi
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
2013-02-14Ruby: Fix compilation errors on gcc 4.7 and clang 3.2Andreas Hansson
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
2013-02-10ruby: enable multiple clock domainsNilay Vaish
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
2013-02-10ruby: replace Time with Cycles in garnet fixed and flexibleNilay Vaish
2013-02-10ruby: replace Time with Tick in replacement policy classesNilay Vaish
2013-02-10ruby: convert block size, memory size to unsignedNilay Vaish
2013-02-10ruby: replace Time with Cycles in MessageBufferNilay Vaish
2013-02-10ruby: replace Time with Cycles in Memory ControllerNilay Vaish
2013-02-10ruby: Replace Time with Cycles in SequencerMessageNilay Vaish
2013-02-10ruby: replace Time with Cycles in Message classNilay Vaish
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
2013-02-10base: add some mathematical operators to Cycles classNilay Vaish
2013-02-10ruby: modifies histogram add() functionNilay Vaish
2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
2013-01-31sim: remove unused struct priority_compareNilay Vaish
2013-01-31ruby: correct computation of number of bits required for addressNilay Vaish
2013-01-31mem: Add comments for the DRAM address decodingAndreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
2013-01-31mem: Separate out the different cases for DRAM bus busy timeAndreas Hansson
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-28ruby: remove get_time()Nilay Vaish
2013-01-28ruby: remove call to curCycle in panic()Nilay Vaish
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22o3 cpu: fix zero reg problemAndrea Pellegrini
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
2013-01-19O3 IEW: Make incrWb and decrWb clearerJoel Hestness
2013-01-17ruby: remove calls to g_system_ptr->getTime()Nilay Vaish
2013-01-15x86 cpuid: enable clflushNilay Vaish
2013-01-15x86: implements fsin, fcos instructionsNilay Vaish
2013-01-15x86: implements emms instructionNilay Vaish
2013-01-15x86: implement fabs, fchs instructionsNilay Vaish
2013-01-14ruby sequencer: converts cycles to ticks in deadlock panic()Malek Musleh
2013-01-14Ruby: remove reference to g_system_ptr from class MessageNilay Vaish
2013-01-14Ruby: use ClockedObject in Consumer classNilay Vaish
2013-01-14scons: Address clang 3.2 compilation errorAndreas Hansson
2013-01-12base simple cpu: removes commented out code about cache opsNilay Vaish