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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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Age
Commit message (
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Author
2012-05-10
Cache: restructure code that actually isn't a loop
Ali Saidi
2012-05-10
dev: use correct delete operation in SimpleDisk
Ali Saidi
2012-05-10
ARM: Fix incorrect use of not operators in arm devices
Ali Saidi
2012-05-10
gem5: assert before indexing intro arrays to verify bounds
Ali Saidi
2012-05-10
gem5: fix some iterator use and erase bugs
Ali Saidi
2012-05-10
gem5: fix a number of use after free issues
Ali Saidi
2012-05-10
base: fix a invalid ?: operator
Ali Saidi
2012-05-10
gem5: Fix a number of incorrect case statements
Ali Saidi
2012-05-10
stats: track if the stats have been enabled and prevent requesting master id
Ali Saidi
2012-05-10
Cache: Panic if you attempt to create a checkpoint with a cache in the system
Ali Saidi
2012-05-10
IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.
Pritha Ghoshal
2012-05-09
stats: use nan instead of no_value
Nathan Binkert
2012-05-09
MEM: Add the communication monitor
Andreas Hansson
2012-05-08
MEM: Do not forward uncacheable to bus snoopers
Andreas Hansson
2012-05-04
Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
Andreas Hansson
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-29
X86: Fix the IMUL_R_P_I macroop.
Gabe Black
2012-04-29
X86: Fix up the open system call's flags.
Vince Weaver
2012-04-29
X86: Make gem5 ignore a bunch of syscalls.
Vince Weaver
2012-04-28
Garnet: Correct computation of link utilization
Nilay Vaish
2012-04-25
Ruby: Remove extra statements from Sequencer
Nilay Vaish
2012-04-25
MEM: Use base class Master/SlavePort pointers in the bus
Andreas Hansson
2012-04-25
MEM: Add the PortId type and a corresponding id field to Port
Andreas Hansson
2012-04-25
clang/gcc: Use STL hash function for int64_t and uint64_t
Andreas Hansson
2012-04-24
X86: Clear out duplicate TLB entries when adding a new one.
Gabe Black
2012-04-23
ISA: Put parser generated files in a "generated" directory.
Gabe Black
2012-04-22
base: Include cassert in trie.hh.
Gabe Black
2012-04-21
X86: Report an error if there's no kernel object, don't blindly use it.
Gabe Black
2012-04-15
CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
Gabe Black
2012-04-15
X86: Fix a tiny typo in the load/store microop constructor.
Gabe Black
2012-04-14
X86: Use the AddrTrie class to implement the TLB.
Gabe Black
2012-04-14
sim: Update some comments in trie.hh that were meant to go in the last change.
Gabe Black
2012-04-14
sim: A trie data structure specifically to speed up paging lookups.
Gabe Black
2012-04-14
Ruby: Use MasterPort base-class pointers where possible
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-04-14
Regression: Add ANSI colours to highlight test status
Andreas Hansson
2012-04-14
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
Andreas Hansson
2012-04-13
SCons: restore Werror option in src/SConscript
Steve Reinhardt
2012-04-12
Ruby: Ensure order-dependent iteration uses an ordered map
Andreas Hansson
2012-04-09
tests: Fix building unit tests.
Gabe Black
2012-04-06
rubytest: remove spurious printf
Brad Beckmann
2012-04-06
slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
Lisa Hsu
2012-04-06
sim-ruby: checkpointing fixes and dependent eventq improvements
Brad Beckmann
2012-04-06
slicc: fixed error message when the type has no inheritance
Brad Beckmann
2012-04-06
MOESI_hammer: tbe allocation and dependent wakeup fixes
Brad Beckmann
2012-04-06
python: added __nonzero__ function to SimObject Bool params
Brad Beckmann
2012-04-06
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...
Brad Beckmann
2012-04-06
rubytest: seperated read and write ports.
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
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