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AgeCommit message (Expand)Author
2012-05-10ARM: guard masked symbol tables by defaultDam Sunwoo
2012-05-10mem: fix bug with CopyStringOut and null string termination.Ali Saidi
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10dev: use correct delete operation in SimpleDiskAli Saidi
2012-05-10ARM: Fix incorrect use of not operators in arm devicesAli Saidi
2012-05-10gem5: assert before indexing intro arrays to verify boundsAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: fix a number of use after free issuesAli Saidi
2012-05-10base: fix a invalid ?: operatorAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10stats: track if the stats have been enabled and prevent requesting master idAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-10IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.Pritha Ghoshal
2012-05-09stats: use nan instead of no_valueNathan Binkert
2012-05-09MEM: Add the communication monitorAndreas Hansson
2012-05-08MEM: Do not forward uncacheable to bus snoopersAndreas Hansson
2012-05-04Ruby: Ensure snoop requests are sent using sendTimingSnoopReqAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-29X86: Fix the IMUL_R_P_I macroop.Gabe Black
2012-04-29X86: Fix up the open system call's flags.Vince Weaver
2012-04-29X86: Make gem5 ignore a bunch of syscalls.Vince Weaver
2012-04-28Garnet: Correct computation of link utilizationNilay Vaish
2012-04-25Ruby: Remove extra statements from SequencerNilay Vaish
2012-04-25MEM: Use base class Master/SlavePort pointers in the busAndreas Hansson
2012-04-25MEM: Add the PortId type and a corresponding id field to PortAndreas Hansson
2012-04-25clang/gcc: Use STL hash function for int64_t and uint64_tAndreas Hansson
2012-04-24X86: Clear out duplicate TLB entries when adding a new one.Gabe Black
2012-04-23ISA: Put parser generated files in a "generated" directory.Gabe Black
2012-04-22base: Include cassert in trie.hh.Gabe Black
2012-04-21X86: Report an error if there's no kernel object, don't blindly use it.Gabe Black
2012-04-15CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.Gabe Black
2012-04-15X86: Fix a tiny typo in the load/store microop constructor.Gabe Black
2012-04-14X86: Use the AddrTrie class to implement the TLB.Gabe Black
2012-04-14sim: Update some comments in trie.hh that were meant to go in the last change.Gabe Black
2012-04-14sim: A trie data structure specifically to speed up paging lookups.Gabe Black
2012-04-14Ruby: Use MasterPort base-class pointers where possibleAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-13SCons: restore Werror option in src/SConscriptSteve Reinhardt
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
2012-04-09tests: Fix building unit tests.Gabe Black
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06slicc: Controllers attached to Sequencers no longer have to be named L1Cache.Lisa Hsu
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
2012-04-06slicc: fixed error message when the type has no inheritanceBrad Beckmann
2012-04-06MOESI_hammer: tbe allocation and dependent wakeup fixesBrad Beckmann
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...Brad Beckmann
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