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AgeCommit message (Expand)Author
2007-01-20fix InterruptLevel code to return the correct levelAli Saidi
2007-01-20atually set all 64 bits of the retun value to 0Ali Saidi
2007-01-20fix flushw implementationAli Saidi
2007-01-20Rearange tlb code to remove some duplicateAli Saidi
2007-01-20Spill and Fill handlers are actually n*4 + the start addressAli Saidi
2007-01-17Allow ASI_LDTX_REALAli Saidi
2007-01-17do a linear search for matching tlb entries instead of using map because you ...Ali Saidi
2007-01-17Implement reading writing of sync fault status register and address registerAli Saidi
2007-01-16In the case that we generate a fault (e.g. a tlb miss) on a microcoded instru...Ali Saidi
2007-01-16Don't add symbols for loaded files to symbol table since they are pretty much...Ali Saidi
2007-01-16Fix legion lock code a bit so that if we jump out of a micro coded instructio...Ali Saidi
2007-01-16In the case of ASI_P or ASI_LDTX_P set primary and skip the other checksAli Saidi
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
2007-01-10bug fixes to get us to 145m instructionsAli Saidi
2007-01-09quiet/remove some warningsAli Saidi
2007-01-09add memory mapped disk deviceAli Saidi
2007-01-08change when legion-lock causes the simulation to die. It now happens after tw...Ali Saidi
2007-01-08fix softint and partially implement hstick interrupts need to figure out how ...Ali Saidi
2007-01-05set the softint appropriately on an timer compare interruptAli Saidi
2007-01-04Merge zizzer:/bk/newmemAli Saidi
2007-01-04Fix stick compare to work correctly and set checkInterrupts to true at the ap...Ali Saidi
2007-01-03set __name__ in the root m5 script to __m5_main__ so we canNathan Binkert
2007-01-03FormattingNathan Binkert
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
2006-12-30Fix up previous commit to proper logic.Kevin Lim
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-29FormattingNathan Binkert
2006-12-27Merge zizzer:/bk/newmemAli Saidi
2006-12-27Bug fixes in the TLBAli Saidi
2006-12-27Compare legion and m5 tlbs for differencesAli Saidi
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
2006-12-27No need to use NULL, just use 0Nathan Binkert
2006-12-26Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.Kevin Lim
2006-12-24Make sure that all of the bits in the result are setNathan Binkert
2006-12-24remove some output formatting stuff that we don't useNathan Binkert
2006-12-21Fix copyrightNathan Binkert
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
2006-12-21styleNathan Binkert
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-12-20Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
2006-12-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-12-19Merge zizzer:/bk/newmemAli Saidi
2006-12-19fix twinx loads a little bitAli Saidi
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
2006-12-18Fix unittest compilesNathan Binkert
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