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2011-05-02ruby: dbg: use system ticks instead of cyclesKorey Sewell
2011-04-28network: set the ExtLink bw to 16 bytesBrad Beckmann
Therefore all links by default are 16 bytes wide and thus work with Garnet's uniform link bandwidth assumption.
2011-04-28garnet: removed flit_width from RoutersBrad Beckmann
2011-04-28network: adjusted default endpoint bandwidthBrad Beckmann
The simple network's endpoint bandwidth value is used to adjust the overall bandwidth of the network. Specifically, the ration between endpoint bandwidth and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value to 1000, that means the bandwdith factor specified in the links translates to the link bandwidth in bytes. Previously, it was increasing that value by 10. This patch will likely require a reset of the ruby regression tester stats.
2011-04-28network: removed the unused network-wide latency paramBrad Beckmann
2011-04-28network: moved network config paramsBrad Beckmann
Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters.
2011-04-28network: basic link bw for garnet and simple networksBrad Beckmann
This patch ensures that both Garnet and the simple networks use the bw value specified in the topology. To do so, the patch generalizes the specification of bw for basic links. This value is then translated to the specific value used by the simple and Garnet networks. Since Garent does not support non-uniformed link bandwidth, the patch also adds a check to ensure all bws are equal. --HG-- rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-28garnet: cleaned up flexible network header fileBrad Beckmann
2011-04-28ruby: moved topology to the top network directoryBrad Beckmann
Moved the Topology class to the top network directory because it is shared by both the simple and Garnet networks. --HG-- rename : src/mem/ruby/network/simple/Topology.cc => src/mem/ruby/network/Topology.cc rename : src/mem/ruby/network/simple/Topology.hh => src/mem/ruby/network/Topology.hh
2011-04-28ruby: removed dated comment in SimpleNetworkBrad Beckmann
2011-04-28event: fix PythonEventNathan Binkert
order of %includes since they matter for this case
2011-04-25base: include types.hh in base/stats/mysql.hhNilay Vaish
Due to certain changes made via changeset 8229, the compilation was failing in certain cases. The compiler pointed to base/stats/mysql.hh for not naming a certain types like uint64_t. To rectify this, base/types.hh is being included in base/stats/mysql.hh.
2011-04-23X86: When decoding a memory only inst, fault on reg encodings, don't assert.Gabe Black
This change makes the decoder figure out if an instruction that only supports memory is using a register encoding and decodes directly to "Unknown" which will behave appropriately. This prevents other parts of the instruction creation process from seeing the mismatch and asserting.
2011-04-20stats: ensure that stat names are validNathan Binkert
2011-04-20stats: one more name violationNathan Binkert
2011-04-20fix some build problems from prior changesetsNathan Binkert
2011-04-20stats: add user settable separator string for arrayed statsBrad Danofsky
Default is '::', so no visible change unless it is overridden
2011-04-20scons: Allow the build directory live under an EXTRAS directoryBrad Danofsky
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-19python: different import for dealing with demandimportNathan Binkert
2011-04-15unittest: Make unit tests capable of using swig and python, convert stattestNathan Binkert
2011-04-15python: cleanup python code so stuff doesn't automatically happen at startupNathan Binkert
this allows things to be overridden at startup (e.g. for tests)
2011-04-15scons: make a flexible system for guarding source filesNathan Binkert
This is similar to guards on mercurial queues and they're used for selecting which files are compiled into some given object. We already do something similar, but it's mostly hard coded for the m5 binary and the m5 library and I'd like to make it more flexible to better support the unittests
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15debug: create a Debug namespaceNathan Binkert
2011-04-15includes: fix up code after sortingNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-15region: add a utility class for keeping track of regions of some rangeNathan Binkert
This is basically like the range_map stuff in src/base (range already exists in Python). This code is like a set of ranges. I'm using it to keep track of changed lines in source code, but it could be use to keep track of memory ranges and holes in memory regions. It could also be used in memory allocation type stuff. (Though it's not at all optimized.)
2011-04-15SortedDict: add functions for getting ranges of keys, values, itemsNathan Binkert
2011-04-15python: figure out if the m5.internal package exists even with demandimportNathan Binkert
2011-04-13refcnt: Update doxygen commentsNathan Binkert
2011-04-13refcnt: Inline comparison functionsNathan Binkert
2011-04-13main: separate out interact() so it can be used by other functionsNathan Binkert
2011-04-10ARM: Fix checkpoint restoration in ARM_SE.Ali Saidi
2011-04-10ARM: Get rid of some comments/todos that no longer apply.Ali Saidi
2011-04-06ruby: fixes to support more types of RubyRequestsBrad Beckmann
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly.
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode.
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
All the m5op parameters are 64 bits, but we were only sending 32 bits; and the static register indexes were incorrectly specified.
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
The comment in the code suggests that the checking granularity should be 16 bytes, however in reality the shift by 8 is 256 bytes which seems much larger than required.
2011-04-04IDE: Support x86, Alpha, and ARM use of the IDE controller.Ali Saidi
2011-04-04ARM: Fix checkpointing case where PL111 is powered off.Ali Saidi
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