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2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
Add a max time option in seconds and a single system root clock be 1THz configs/test/fs.py: Add a max time option in seconds and a single system root clock be 1THz src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Enforce the timing cpu ticking at it's clock rate --HG-- extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-19Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c5dbee4ba46fae1edba732f4bd05ef984a46d088
2006-07-19Change the device latency here to a latency rather than a TickAli Saidi
src/python/m5/objects/Device.py: src/python/m5/objects/Pci.py: Change the default here to a latency rather than a Tick --HG-- extra : convert_revision : b9366dd89646cea27a836baf249ac2da38c1809f
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
src/cpu/checker/cpu.hh: Don't count checker's instructions towards total instructions committed. src/python/m5/objects/Root.py: Set default clock to 1 THz. --HG-- extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
2006-07-19Put regression tests back into m5. They are located in the "tests" ↵Kevin Lim
directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model> Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files. Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file. Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed. SConstruct: Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again. src/cpu/SConscript: Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only. --HG-- extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
2006-07-19Get the path to load the ini file from. I'm not sure if this fix is needed ↵Kevin Lim
in other places as well. src/sim/main.cc: Get the path to load the ini file from. --HG-- extra : convert_revision : aa38fc9b1bc99cd74d095cbfc67253e4549f91d3
2006-07-19O3CPU fixes.Kevin Lim
src/cpu/o3/lsq_unit.hh: LSQ needs to decrement the WB counter if the load is going to be replayed. src/cpu/o3/lsq_unit_impl.hh: LSQ needs to decrement the WB counter if the load is squashed. --HG-- extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
2006-07-19Some minor compiling fixes.Kevin Lim
src/cpu/o3/iew.hh: Non-debug compile fixes. src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: Merge fix. --HG-- extra : convert_revision : 38081925d2b74d8f64acdb65dba94b2bf465b16a
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: configs/test/test.py: SCCS merged --HG-- extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-14Minor updates.Kevin Lim
src/python/m5/config.py: Formatting. src/python/m5/main.py: Slightly more useful output when you don't enter in a valid script file. --HG-- extra : convert_revision : 5a71a6c94dbedeb000f83f57b0b575c2df924509
2006-07-14Fix the CheckerCPU being included via python.Kevin Lim
src/arch/SConscript: Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified. src/cpu/SConscript: Copy the CPU_MODELS from the env, don't create a proxy to it. --HG-- extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
2006-07-14forgot tidKorey Sewell
--HG-- extra : convert_revision : 272ef8f9cd0802770edc4dcef2c26dc44de71e47
2006-07-14For now, halt context is the same as deallocating.Korey Sewell
suspend context will now take the thread off the activeThread list. src/arch/mips/isa_traits.cc: add in copy MiscRegs unimplemented function --HG-- extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
2006-07-14MIPS specific fixes ... the main thing is that SMT threads get their own ↵Korey Sewell
stack space instead of all stacks start to space src/arch/mips/isa_traits.hh: MaxAddr is defined in config.py now src/arch/mips/process.cc: adjust process so SMT threads get their own stack space src/arch/mips/process.hh: add stack_start static variable --HG-- extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
2006-07-13Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem src/python/m5/main.py: merge two help fixes --HG-- extra : convert_revision : b5c4a88bb84b726bebd3e357a4ef29acc0d95600
2006-07-13fix help when no arguments are passed to m5Ali Saidi
--HG-- extra : convert_revision : ee6614166fd5814654309298abe5a706ff02c4c2
2006-07-13add system.mem_mode = ['timing', 'atomic']Ali Saidi
update scripts acordingly configs/test/SysPaths.py: new syspaths from nate, this one allows you to set script, binary, and disk paths like system.dir = 'aouaou' in your script configs/test/fs.py: update for system mem_mode Put small checkpoint example Make clock 1THz configs/test/test.py: src/arch/alpha/freebsd/system.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/system.cc: src/arch/alpha/tru64/system.cc: src/arch/sparc/system.cc: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: update for system mem_mode src/dev/io_device.cc: Use time returned from sendAtomic to delay --HG-- extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's ↵Kevin Lim
recent changes, and using the O3CPU in SMT mode. src/cpu/o3/lsq.hh: Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked. src/cpu/o3/lsq_impl.hh: Updates to have the LSQ work with only one dcache port for all LSQUnits. src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache. --HG-- extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
2006-07-13Fix for bug when squashing and the fetching. Now fetch checks if the cache ↵Kevin Lim
data is valid. --HG-- extra : convert_revision : 07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
2006-07-13Update for changes to draining.Kevin Lim
--HG-- extra : convert_revision : 5038dd8be72827f40cf89318db0b2bb4f9bbd864
2006-07-13Fix help message printing. Might need to clean up the handling of the ↵Kevin Lim
sys.exit() call, as right now it prints out "None" at the end (not sure why). src/python/m5/main.py: Fix help message printing. --HG-- extra : convert_revision : 6906234101eb7ff7df7933e9aede0362b5a991bd
2006-07-12memory mode information now contained in system objectAli Saidi
States are now running, draining, or drained. memory state information moved into system object system parameter is not fs only for cpus Implement drain() support in devices Update for drain() call that returns number of times drain_event->process() will be called Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: Since se mode has a system, allow access to it Verify that the atomic cpu is connected to an atomic system on resume src/cpu/simple/base.cc: Since se mode has a system, allow access to it src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system Since se mode has a system, allow access to it Verify that the timing cpu is connected to an timing system on resume src/dev/ide_disk.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: src/dev/sinic.cc: src/dev/sinic.hh: Implement drain() support in devices src/python/m5/config.py: Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times src/python/m5/objects/BaseCPU.py: move system parameter out of fs to everyone src/sim/sim_object.cc: src/sim/sim_object.hh: States are now running, draining, or drained. memory state information moved into system object src/sim/system.cc: src/sim/system.hh: memory mode information now contained in system object --HG-- extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/test.py: Hand merge. --HG-- extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
2006-07-12Be sure to include the EIO sources as well so we can run regression tests.Kevin Lim
src/SConscript: It's no longer "ALPHA_ISA". I don't think we meant to leave out the EIO sources. --HG-- extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc
2006-07-12Serialization changes to make O3CPU consistent with the other models.Kevin Lim
src/cpu/o3/commit_impl.hh: Always set instruction. This is necessary for serialization as the instruction is also serialized. src/cpu/o3/cpu.cc: Change serialization so it matches other CPU's output. Also fix up some indexing. --HG-- extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
2006-07-12Push more default options to the Python object level as they are rarely ↵Kevin Lim
changed. These are the changes that Steve was working on. src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/Tsunami.py: Push more default options to the Python object level as they are rarely changed. --HG-- extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
2006-07-12Updates for serialization. As long as the tickEvent doesn't need to be ↵Kevin Lim
serialized (I don't believe it does because we drain all CPUs prior to checkpointing), it should be feasible to start up from other CPU's checkpoints. src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.cc: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: Updates for serialization. --HG-- extra : convert_revision : 0f150de75d4bc833e4c9b83568e7fd22688d5727
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem src/cpu/o3/fetch_impl.hh: Hand merge. --HG-- extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory ↵Kevin Lim
multiple times if information is already in fetch. --HG-- extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
2006-07-12Add --pdbNathan Binkert
src/python/m5/main.py: Add a command line option to invoke pdb on your script --HG-- extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
2006-07-12Merge m5.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/research/m5/current --HG-- extra : convert_revision : 842a23da034c40c75364b76ca75de076da776ac6
2006-07-12Fix __file__ for scriptsNathan Binkert
src/python/m5/main.py: set __file__ to the script, not the m5 binary. --HG-- extra : convert_revision : a0bbd059d2fd321ae8ff68225abc8a7bb5c410ed
2006-07-11Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 3be1aa4892aa8bbd458bdc5538bbcbd6c1ebe299
2006-07-11Fix ordering issue with squashed Icache Fetches and Static data in packet.Ron Dreslinski
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests). src/cpu/o3/fetch_impl.hh: Fix ordering issue with squashed Icache Fetches and Static data in packet. --HG-- extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
2006-07-11Fix option parsing.Nathan Binkert
src/python/m5/main.py: Don't allow interspersed arguments, it messes things up --HG-- extra : convert_revision : 8f1bcf4391f570741d92bf5420879862a48f6016
2006-07-10Migrate most of main() and and all option parsing to pythonNathan Binkert
configs/test/fs.py: configs/test/test.py: update for the new way that m5 deals with options src/python/SConscript: Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the python stuff. src/python/m5/__init__.py: redo the way options work. Move them all to main.py src/sim/main.cc: Migrate more functionality for main() into python. Namely option parsing src/python/m5/attrdict.py: A dictionary object that overrides attribute access to do item access. src/python/m5/main.py: The new location for M5's option parsing, and the main() routine to set up the simulation. --HG-- extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
2006-07-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : c811eb9eacc480b14862f8074af80c56ec1e07f1
2006-07-10Some fixes so that MSHR's are matched and we don't issue overlapping ↵Ron Dreslinski
requests with detailed cpu src/mem/cache/base_cache.cc: If we still have outstanding requests, need to schedule event again src/mem/cache/miss/miss_queue.cc: Need to use block size so overlapping requests match in the MSHR's src/mem/cache/miss/mshr.cc: Actually save the address, otherwise we can't match MSHR's --HG-- extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
2006-07-10Minor fixes.Kevin Lim
src/cpu/checker/thread_context.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: Change functions to match Korey's changes. src/cpu/ozone/lw_back_end.hh: Fix compile error. --HG-- extra : convert_revision : fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6
2006-07-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244
2006-07-10Some minor cleanups.Kevin Lim
src/cpu/SConscript: Change the error message to be slightly nicer. src/cpu/o3/commit.hh: Remove old code. src/cpu/o3/commit_impl.hh: Remove old unused code. --HG-- extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
src/base/timebuf.hh: Add a function to return the size of the time buffer. --HG-- extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-10Fix offset calculation. Now L2's work with timing&atomic.Ron Dreslinski
src/mem/packet.hh: Offset is based on packet, not request. --HG-- extra : convert_revision : d85af5838370541328ca35072c612d8198020625
2006-07-10Fix cpu in full system to match SE.Ron Dreslinski
--HG-- extra : convert_revision : 95e422221ff5bab6104925d50a8882d31729b0f5
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
2006-07-07Support for recent port changes.Kevin Lim
src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. --HG-- extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
2006-07-07Fix for bug when draining and a memory access is outstanding.Kevin Lim
--HG-- extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936
2006-07-07Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766
2006-07-07Take the name of the checkpoint directory in when calling checkpoint() or ↵Kevin Lim
restoreCheckpoint(). src/sim/main.cc: src/sim/serialize.cc: src/sim/serialize.hh: Take in the directory name when checkpointing. --HG-- extra : convert_revision : 040e828622480f1051e2156f4439e24864c38d45
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