| Age | Commit message (Expand) | Author |
|---|
| 2015-05-05 | arm: Add missing FPEXC.EN check | Andreas Hansson |
| 2015-05-05 | arm: enable DCZVA by default in SE mode | Giacomo Gabrielli |
| 2015-03-17 | mem: Create a request copy for deferred snoops | Stephan Diestelhorst |
| 2015-05-05 | arm: Relax ordering for some uncacheable accesses | Andreas Sandberg |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-05-05 | mem, alpha: Move Alpha-specific request flags | Andreas Sandberg |
| 2015-05-05 | arm: Remove unnecessary boot uncachability | Andreas Hansson |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-05-05 | arch, cpu: Do not forward snoops to table walker | Andreas Hansson |
| 2015-05-05 | mem: Pass shared downstream through caches | Andreas Hansson |
| 2015-05-05 | mem: Add forward snoop check for HardPFReqs | Ali Jafri |
| 2015-05-05 | mem: Add missing stats update for uncacheable MSHRs | Andreas Hansson |
| 2015-05-05 | mem: Tidy up BaseCache parameters | Andreas Hansson |
| 2015-05-05 | mem: Remove templates in cache model | David Guillen |
| 2015-05-05 | cpu: Work around gcc 4.9 issues with Num_OpClasses | Andreas Hansson |
| 2015-04-29 | arch, base, dev, kern, sym: FreeBSD support | Ruslan Bukin |
| 2015-04-29 | mem: Simplify page close checks for adaptive policies | Rizwana Begum |
| 2015-04-29 | ruby: set: replace long by unsigned long | Nilay Vaish |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2015-04-29 | cpu: o3: single cycle default div microop latency on x86 | Nilay Vaish |
| 2015-04-29 | x86: change divide-by-zero fault to divide-error | Nilay Vaish |
| 2015-04-24 | misc: Appease gcc 5.1 without moving GDB_REG_BYTES | Andreas Hansson |
| 2015-04-23 | arm, dev: Add a UFS device | Rene de Jong |
| 2015-04-23 | arm, dev: Add a NAND flash timing model | Rene de Jong |
| 2015-04-23 | dev: Add support for i2c devices | Peter Enns |
| 2015-04-23 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-04-22 | cpu: remove conditional check (count > 0) on o3 IQ squashes | Brandon Potter |
| 2015-04-22 | syscall_emul: implement clock_gettime system call | Brandon Potter |
| 2015-04-22 | syscall_emul: update x86 syscall table | Monir Mozumder |
| 2015-04-22 | syscall_emul: update getrlimit to use warn | Brandon Potter |
| 2015-04-22 | syscall_emul: fix warning with wrong syscall name | Brandon Potter |
| 2015-04-22 | base: add new ChunkGenerator method to identify last chunk | Brandon Potter |
| 2015-04-20 | cpu: Remove the InOrderCPU from the tree | Andreas Hansson |
| 2015-04-14 | config, cpu: fix progress interval for switched CPUs | Malek Musleh |
| 2015-04-13 | cpu: re-organizes the branch predictor structure. | Dibakar Gope |
| 2015-04-13 | x86: implements x87 mult/div instructions | Nilay Vaish |
| 2015-04-13 | ruby: allow restoring from checkpoint when using DRAMCtrl | Lena Olson |
| 2015-04-13 | sim: Use NULL instead of None for testing filenames. | Nilay Vaish |
| 2015-04-13 | sim: fix function for emulating dup() | Nilay Vaish |
| 2015-04-08 | config: Support full-system with SST's memory system | Curtis Dunham |
| 2015-04-03 | dev: (un)serialize fix for the RTC and RTC Timer Interrupt events | Nikos Nikoleris |
| 2015-04-03 | sim: correct check for endianess | Ruslan Bukin |
| 2015-04-03 | dev: Extend access width for IDE control registers | Ruslan Bukin |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-04-03 | x86: fix debug trace output for mwait | Lena Olson |
| 2015-03-27 | mem: Support any number of master-IDs in stride prefetcher | Stephan Diestelhorst |
| 2015-03-27 | mem: Allocate cache writebacks before new MSHRs | Andreas Hansson |
| 2015-03-27 | mem: Cleanup flow for uncacheable accesses | Andreas Hansson |
| 2015-03-27 | mem: Ignore uncacheable MSHRs when finding matches | Andreas Hansson |
| 2015-03-27 | mem: Remove redundant allocateUncachedReadBuffer in cache | Andreas Hansson |
