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AgeCommit message (Expand)Author
2013-04-17dev: Fix a bug in the use of seekp/seekgAndreas Hansson
2013-04-09Ruby: Fix RubyPort evict packet memory leakJoel Hestness
2013-04-09Ruby: Delete packet requests during warmupJoel Hestness
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
2013-04-09Ruby: Order profilers based on versionJoel Hestness
2013-04-09Ruby: More descriptive message buffer connection fatalJason Power
2013-04-09Ruby: Fix typo in Slicc if-statement AST errorJason Power
2013-04-07Ruby System, Cache Recorder: Use delete [] for trace varsJoel Hestness
2013-03-29o3cpu: commit: changes interrupt handlingNilay Vaish
2013-03-28x86: changes to apic, keyboardNilay Vaish
2013-03-27mem: Fix cache latency bugMitch Hayenga
2013-03-27scons: don't die on warnings in swig-generated codeSteve Reinhardt
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-03-26mem: Introduce a variable for the retrying portAndreas Hansson
2013-03-26mem: Add a generic id field to the packet traceAndreas Hansson
2013-03-26mem: Add optional request flags to the packet traceAndreas Hansson
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-03-22ruby: slicc: set sender, receiver clock objs for optional queueNilay Vaish
2013-03-22ruby: message buffer: correct previous errorsNilay Vaish
2013-03-22ruby: message buffer: remove _ptr from some variablesNilay Vaish
2013-03-22ruby: message buffer node: used Tick in place of CyclesNilay Vaish
2013-03-22ruby: consumer: avoid using receiver side clockNilay Vaish
2013-03-22ruby: remove unsued profile functionsNilay Vaish
2013-03-22ruby: keep histogram of outstanding requests in seqNilay Vaish
2013-03-22slicc: remove check if the L1Cache has a sequencerNilay Vaish
2013-03-22ruby: move stall and wakeup functions to AbstractControllerNilay Vaish
2013-03-22ruby: connect two controllers using only message buffersNilay Vaish
2013-03-22ruby: convert Topology to regular classNilay Vaish
2013-03-22ruby: network: move routers from topology to networkNilay Vaish
2013-03-20cpu: Avoid including inorder TLBUnit to avoid gcc LTO bugAndreas Hansson
2013-03-18mem: Fix missing delete of packet in DRAM accessAndreas Hansson
2013-03-15ruby: set: corrects csprintf() call introduced by 7d95b650c9b6Nilay Vaish
2013-03-12cpu: Fix state transition bug in the traffic generatorAndreas Sandberg
2013-03-11x86: implement some of the x87 instructionsNilay Vaish
2013-03-07base: Fix address range granularity calculationsAndreas Hansson
2013-03-07ruby: Fix gcc 4.8 maybe-uninitialized compilation errorAndreas Hansson
2013-03-07x86: Make the table walker reset the packet delayAndreas Hansson
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-03-06ruby: garnet: fixed: implement functional accessNilay Vaish
2013-03-04cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-03-04ARM: fix some cases where instructions that write to fp reg 15 are accidently...Ali Saidi
2013-03-02ruby: fixes functional writes to RubyRequestBlake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-02sim: remove duplicate check on stack sizeNilay Vaish
2013-03-01mem: Add check if SimpleDRAM nextReqEvent is scheduledAndreas Hansson
2013-03-01mem: Add a method to build multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: SimpleDRAM variable naming and whitespace fixesAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: Merge interleaved ranges when creating backing storeAndreas Hansson
2013-03-01mem: Merge ranges in bus before passing them onAndreas Hansson