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AgeCommit message (Expand)Author
2017-11-16ext, mem: Pull DRAMPower SHA 90d6290 and rebaseRadhika Jagtap
2017-11-16pwr: Enable multiple power models per componentDavid Guillen Fandos
2017-11-16arch, arm: Print value being ignored on DummyISA writeSean McGoogan
2017-11-16sim: Clocked object debug message updated for clarityTiago Muck
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
2017-11-15arch-arm: Dsb instruction shouldn't flush the pipelineGiacomo Travaglini
2017-11-15arch-arm: Writes to DCCMVAC shouldn't flush pipelineGiacomo Travaglini
2017-11-15arch-arm: Removing FlushPipe fault, using SquashAfterGiacomo Travaglini
2017-11-15arm: Add support for armv8 CRC32 instructionsGiacomo Travaglini
2017-11-14cpu, probe: Fix elastic trace register dependencyRadhika Jagtap
2017-11-13config: Add an Energy param type.Gabe Black
2017-11-13config: Export the "Current" param type from m5.params.Gabe Black
2017-11-13util: Add a "toEnergy" function to the convert module.Gabe Black
2017-11-13config: Simplify the definitions of the Voltage and Current params.Gabe Black
2017-11-13arch-arm: Interface for the ArmStaticInst intWidth fieldGiacomo Travaglini
2017-11-13arch-arm: Corrected encoding for T32 HVC instructionGiacomo Travaglini
2017-11-13util: Simplify/consolidate the python conversion module.Gabe Black
2017-11-10scons: Move Transform and termcap functionality into their own files.Gabe Black
2017-11-09mem: Align the snoop behavior in the XBar for atomic and timingNikos Nikoleris
2017-11-09arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1Nikos Nikoleris
2017-11-08dev: Move generic serial devices to src/dev/serialAndreas Sandberg
2017-11-08dev: Add a dummy serial deviceAndreas Sandberg
2017-11-08dev: Refactor UART->Terminal interfaceAndreas Sandberg
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
2017-11-06sim-se: Add prlimit system callAlec Roelke
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
2017-10-31dev: Using Configurable image writer in HDLcdGiacomo Travaglini
2017-10-31vnc: Default image writer type set to AutoGiacomo Travaglini
2017-10-31base: Introducing utility for writing raw data in png formatGiacomo Travaglini
2017-10-31x86: Fix VEX instruction decoding.Gabe Black
2017-10-30base: Fix forcing loopback only binding for listeners.Gabe Black
2017-10-20arch-arm: RBIT instruction using mirroring funcGiacomo Travaglini
2017-10-20base: Function for mirroring bits in variable length wordGiacomo Travaglini
2017-10-20base: Defining make_unique for C++11Giacomo Travaglini
2017-10-19cpu-o3: Add M5_VAR_USED to variableJason Lowe-Power
2017-10-19scons: Fix the regression tests.Gabe Black
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
2017-10-17arch-arm: Fix inverted 32/64-bit check in GDBBoris Shingarov
2017-10-13arch-arm: Signal an event when executing store exclusivesNikos Nikoleris
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
2017-09-26util: Make dot_writer ignore NULL simobjects.Gabe Black
2017-09-26dev: Make the IDE controller handle NULL simobject pointers.Gabe Black
2017-09-26sim: Add a get_config_as_dict to the NullSimObject class.Gabe Black
2017-09-26sim: Don't add the NULL SimObject as a child of other SimObjects.Gabe Black