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AgeCommit message (Expand)Author
2013-03-22ruby: consumer: avoid using receiver side clockNilay Vaish
2013-03-22ruby: remove unsued profile functionsNilay Vaish
2013-03-22ruby: keep histogram of outstanding requests in seqNilay Vaish
2013-03-22slicc: remove check if the L1Cache has a sequencerNilay Vaish
2013-03-22ruby: move stall and wakeup functions to AbstractControllerNilay Vaish
2013-03-22ruby: connect two controllers using only message buffersNilay Vaish
2013-03-22ruby: convert Topology to regular classNilay Vaish
2013-03-22ruby: network: move routers from topology to networkNilay Vaish
2013-03-20cpu: Avoid including inorder TLBUnit to avoid gcc LTO bugAndreas Hansson
2013-03-18mem: Fix missing delete of packet in DRAM accessAndreas Hansson
2013-03-15ruby: set: corrects csprintf() call introduced by 7d95b650c9b6Nilay Vaish
2013-03-12cpu: Fix state transition bug in the traffic generatorAndreas Sandberg
2013-03-11x86: implement some of the x87 instructionsNilay Vaish
2013-03-07base: Fix address range granularity calculationsAndreas Hansson
2013-03-07ruby: Fix gcc 4.8 maybe-uninitialized compilation errorAndreas Hansson
2013-03-07x86: Make the table walker reset the packet delayAndreas Hansson
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-03-06ruby: garnet: fixed: implement functional accessNilay Vaish
2013-03-04cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-03-04ARM: fix some cases where instructions that write to fp reg 15 are accidently...Ali Saidi
2013-03-02ruby: fixes functional writes to RubyRequestBlake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-02sim: remove duplicate check on stack sizeNilay Vaish
2013-03-01mem: Add check if SimpleDRAM nextReqEvent is scheduledAndreas Hansson
2013-03-01mem: Add a method to build multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: SimpleDRAM variable naming and whitespace fixesAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: Merge interleaved ranges when creating backing storeAndreas Hansson
2013-03-01mem: Merge ranges in bus before passing them onAndreas Hansson
2013-02-28ruby: mesi coherence protocol: invalidate lockDibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-02-19slicc: remove unused variable message_buffer_namesNilay Vaish
2013-02-19ruby: remove unused variable m_print_config in class TopologyNilay Vaish
2013-02-19mem: Fix sender state bug and delay poppingAndreas Hansson
2013-02-19scons: Fix warnings issued by clang 3.2svn (XCode 4.6)Andreas Hansson
2013-02-19scons: Unify the flags shared by gcc and clangAndreas Hansson
2013-02-19scons: Add warning delete with non-virtual destructorAndreas Hansson
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for missing field initializersAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-19base: Fix a bug in the address interleavingAndreas Hansson
2013-02-19mem: Ensure trace captures packet fields before forwardingAndreas Hansson
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