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These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.
Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I14ccb0655819887db2306fee1188e1c83a991743
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/11669
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
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There are cases where we need to limit the symbol visibility to avoid
compilation errors. This is a problem for Python code that relies on
PyBind11 since recent versions enforce hidden symbols. As a
consequence, classes that have member variables from PyBind11 need to
be declared with the hidden attribute (or gem5 needs to be compiled
with -fvisibility=hidden).
Change-Id: I30e582fde494ff61ab7a596a595efc26a2952a5f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11513
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ifa9efbd329fd01eb13100bc6690e651df2c12294
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11514
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ie81104d89b554795ec1020d5ce4edcf28795eda8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:
* delayReq(pkt)
* delayResp(pkt)
* delaySnoopResp(pkt)
These methods should be specialized to implement delays for specific
packet types.
The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.
The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.
Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.
Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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This patch is providing gem5 a Coroutine class to be used for
instantiating asymmetrical coroutines. Coroutines are built on top of
gem5 fibers, which makes them ucontext based.
Change-Id: I7bb673a954d4a456997afd45b696933534f3e239
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11195
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This sets the members of a Request object to the values they
already hold, except the atomicOpFunctor which is set to
nullptr. This call introduces a bug for atomics and is not
useful for non-atomic requests. This changeset is also
adding the wave PC and instruction sequence number to the
Request object.
Change-Id: I62f7b4a597483b0aa848a0cfbc72181e1063f56a
Reviewed-on: https://gem5-review.googlesource.com/11549
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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Previously we allowed multiplications between proxy Param and
compatible constants (int, long, float). This change extends this
functionality and adds support for multiplying with between proxy
Param and compatible proxy Param.
Change-Id: I23a083881ae4d770e818895b893534767cd2472d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11510
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Building gem5 binaries or regression test binaries needs to be done
from within the make_env function which builds an environment for each
flavor of build (opt, fast, debug, etc.). That makes it impossible to
add new types of binaries without modifying the central SConscript.
This change refactors how binaries are set up so that the class that
represents them handles the details of how the binary should be built.
Also, a metaclass and some lists track types of binaries and individual
instances of binaries so that they can be iterated over automatically
in make_env.
Each new executable class can define a declare_all class function which
calls declare() on individual instances. declare_all is a place to do
any processing that only has to happen once (for instance specializing
the environment) for a particular family of executables.
Change-Id: I8a6ee9438280cd67e6c0b92ca28738a53cb16950
Reviewed-on: https://gem5-review.googlesource.com/10915
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Iebda05c130b4d2ee8434cad1e703933bfda486c8
Reviewed-on: https://gem5-review.googlesource.com/11490
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: If8922c2233bbe1f6fce35f64d1a44b91d2cfeed2
Reviewed-on: https://gem5-review.googlesource.com/11489
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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While a cache clean operation is pending, all requests to the
corresponding block get deferred. When the response of a cache clean
operation is received, if the block is present and the response is not
invalidating, we can service all deferred targets that didn't require
writable. This change implements this functionality.
Change-Id: Ief47e74d07749a6a9736ab450eb46eefa53464a2
Reviewed-on: https://gem5-review.googlesource.com/11018
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. Due to the way we handle cache
clean operations we might need to promote only deferred targets that
don't require writable, leaving some targets as deferred. This change
adds support for this selective promotion.
Change-Id: I502e523dc9adbaf394955cbacea8286ab6a9b6bc
Reviewed-on: https://gem5-review.googlesource.com/11017
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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There are cases where a request which does not need a writable copy
gets an response upgraded reponse and fills in a writable copy. When
this happens, we promote deferred MSHR targets that were deferred
because they needed a writable copy to service them immediately.
Previously, we would uncoditionally promote deferred targets. Since
the deferred targets might contain a cache invalidation operation, we
have to make sure that any targets following the cache invalidation is
not promoted.
Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a
Reviewed-on: https://gem5-review.googlesource.com/11016
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. When we promote deferred targets
we also clear the downstreamPending flag.
Due to the way we handle cache clean operations we might need to
promote only deferred targets that don't require writable, leaving
some targets as deferred. To allow for partial target promotion, this
change adds support for clearing the downstreamPending only for a
subset of a TargetsList.
Change-Id: Id06953643ba9a975ebacc76ac10215441e264e74
Reviewed-on: https://gem5-review.googlesource.com/11015
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when
interprocessing if the trapping conditions are met.
Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11197
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The old utility function called badMode was only checking if the mode
passed as an argument was a recognized mode. It was not checking if the
corresponding mode/EL was implemented. That function has been renamed to
unknownMode and a new badMode has been introduced. This is used by the
cpsrWriteByInstruction function. In this way any try to change the
execution mode won't succeed if the mode hasn't been implemented.
Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11196
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This class encapsulates the idea of a Fiber in such a way that other
implementations can be substituted in in the future. This
implementation uses the ucontext family of functions.
This change also adds a new unit test which exercises the new class. It
creates three new fibers which accept a sequence of other fibers to
switch to, one after the other. The main test function switches to
the these fibers which switch with each other and occasionally back to
the main fiber. Each time a test fiber is activated, it checks against
a list which shows the correct order for the fibers to run in. When the
main fiber gets control, it makes sure that list has been progressed
through by the correct amount.
Change-Id: I1fc2afa414b51baaa91e350a4ebc791d989f0b8a
Reviewed-on: https://gem5-review.googlesource.com/10935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Instead of using a convoluted getattr call, use the conventional
iteritems() interface.
Change-Id: I6d6bbccf865f8a0e8ff0767914157a7460099b09
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10782
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The platform code uses a custom mechanism to traverse the object
hierarchy when generating device trees. This is highly undesirable
since this breaks for common cases such as when SimObjects are stored
in a list.
Change-Id: I1b968e5fa1db62f1456e3c0ac3de47ab1299e58d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10781
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Missing buffer allocation in mwaitAtomic.
Change-Id: Ifccb6df2427df8b0daac5ee6a99e5cca0b20825e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I4bdd6cf7c8d22219c0582ab206ec8372a4357759
Reviewed-on: https://gem5-review.googlesource.com/11429
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.
Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11349
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Previously, we used the start address to determine the right physical
memory while servicing memory requests. This change uses the full
address range to correctly determine the right physical memory and
expose bugs where requests might not fully map to a single physical
memory.
Change-Id: I183d7552918106000f917a62ceb877511ff0ff71
Reviewed-on: https://gem5-review.googlesource.com/11118
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Previously the xbar used the start address to lookup the port map and
determine the right destination of an incoming packet. This change
uses the full address range to correctly determine the right master.
Change-Id: I5118712c43ae65aba64e71bf030bca5c99770bdd
Reviewed-on: https://gem5-review.googlesource.com/11117
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Use it instead of custom implemented caching.
Change-Id: Ie21012a77a3cb6ce57f34f879fa391678913896a
Reviewed-on: https://gem5-review.googlesource.com/5244
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Use that instead of caching built into the crossbar.
Change-Id: If5a5355a0a1a6e532b14efc88a319de4c023f8c1
Reviewed-on: https://gem5-review.googlesource.com/5243
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Rather than have each consumer of the AddrRangeMap implement caching
lookups on their own, this change adds a centralized mechanism to the
AddrRangeMap class itself.
Some benefits of this approach are that the cache handles deleted
entries correctly/automatically, the cache is maintained by
adding/removing entries from a linked list rather than moving elements
in an array and checking valid bits, and it's easy to enable in places
which might otherwise not bother with caching. The amount of caching
is tunable to balance overhead with improved lookup performance.
Change-Id: Ic25997e23de4eea501e47f039bb52ed0502c58d2
Reviewed-on: https://gem5-review.googlesource.com/5242
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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We need to determined whether an address range is fully contained or
it overlaps with an address range in the address range in the mmap. As
an example, we use address range maps to associate ports to address
ranges and we determine which port we will forward the request based
on which address range contains the addresses accessed by the
request. We also need to make sure that when we add a new port to the
address range map, its address range does not overlap with any of the
existing ports.
This patch splits the function find() into two functions contains()
and intersects() to implement this distinct functionality. It also
changes the xbar and the physical memory to use the right function.
Change-Id: If3fd3f774a16b27db2df76dc04f1d61824938008
Reviewed-on: https://gem5-review.googlesource.com/11115
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Fully associative caches use an unordered map to enable efficient
lookups of existing blocks. Previously this map was indexed using the
tag of the block. Security extentions allow secure and non secure
versions of a block with the same tag to co-exist in the cache. This
patch amends the block map to allow correct lookups for FALRU caches.
Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556
Reviewed-on: https://gem5-review.googlesource.com/11309
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Initialize CacheBlk's data pointer as a nullptr.
Change-Id: Ice85b4b11495cad4b0a160ccb9efe1be673e57e2
Reviewed-on: https://gem5-review.googlesource.com/11097
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Forward declare ReplaceableEntry where in classes where pointers
to it are used.
Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60
Reviewed-on: https://gem5-review.googlesource.com/11096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Previously, many devices were incorrecty configured to respond to an
address range of size 0xfff. This changes fixes this and sets it to
0x1000.
Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11116
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The base for the c++ version of python SimObject classes is normally
inferred from the c++ version of the python base. There are some
specific cases where that isn't desired. This change makes it possible
to override the default behavior.
Change-Id: I2438dad767e2f56823bad42b3e6c7714ce97ef79
Reviewed-on: https://gem5-review.googlesource.com/10662
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.
This patch added a status check before a CPU schedule a fetch event
after a fault is handled.
Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Reviewed-on: https://gem5-review.googlesource.com/8181
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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This patch adds a new flag named 'Atomic' to support ISA implementations
that use AtomicOpFunctor to handle atomic instructions instead of a
pair of locking load and unlocking store.
Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115
Reviewed-on: https://gem5-review.googlesource.com/8187
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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This patch adds two new functions named amoMemAtomic used in Atomic CPU
model and initiateMemAMO used in Timing CPU models to issue AMO requests
to the memory system.
Change-Id: I962bdc0e5f25b72c170d96ebc136f29a2b230d5e
Reviewed-on: https://gem5-review.googlesource.com/8186
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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AtomicOpFunctor can be used to implement atomic memory operations.
AtomicOpFunctor is captured inside a memory request and executed directly
in the memory hierarchy in a single step.
This patch enables AtomicOpFunctor pointers to be included in a memory
request and executed in a single step in the classic cache system.
This patch also makes the copy constructor of Request class do a deep
copy of AtomicOpFunctor object. This prevents a copy of a Request object
from accessing a deleted AtomicOpFunctor object.
Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37
Reviewed-on: https://gem5-review.googlesource.com/8185
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.
Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/10561
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The Illegal Execution fault triggered by the setting of processor state
PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED
exception fault. We are hence copying the UndefinedInstruction AArch32
fields into the IllegalInstSetStateFault.
Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage. This is
done by adding the illegalExecution field to the PCState.
Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.
Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Add a new VExpress_GEM5_V1_Base Platform which configures basic on
chip devices. The original VExpress_GEM5_V1 will inherit the Base and
add more on chip devices (currently only the HDLCD). This change will
make it possible to create variations of the base platform with
different devices.
Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10807
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Don't call startup() twice on each of the threads.
Change-Id: Ibe3d1f25c4fdff291ee310abb9bcad3b184bab20
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11037
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Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10810
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The original implementation of UnitTest forced all the output binaries
to live in the unittest directory, effectively forcing a flat
namespace, and seperating the tests from the things they were supposed
to be testing.
This changes makes them work more like the newer GTest tests in that
they can be based out of whatever directory makes sense, although
they're currently all still in unittest for the time being.
This change also gets rid of automatically tagging the sources
associated with a test with the tests name. The first reason for that
was that this also forced a flat namespace, since the tests names
didn't have any reference to the test's path. Second, this way of
pulling in additional files wasn't necessary any more, now that the
UnitTest sources could be source filters like they can be for GTests.
Change-Id: I3d96ed766ac5170842dbd6daee39f2873bcd6c75
Reviewed-on: https://gem5-review.googlesource.com/10701
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Removes an uneccessary cast that also caused an unused variable
error (due to -Werror) when compiling .fast targets.
Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980
Reviewed-on: https://gem5-review.googlesource.com/11119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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