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2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
Change-Id: I2a146ae57aac3787389997961208474a97e7c155 Reviewed-on: https://gem5-review.googlesource.com/3360 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-16x86: Fix the multiplication microops.Gabe Black
If the operands were 64 bit, an intermediate calculation could lose a carry bit. This change rearranges that intermediate calculation if the operand width is large, and reworks the microop implementation in general in an attempt to make it easier to understand. Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea Reviewed-on: https://gem5-review.googlesource.com/3381 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-16python: Add a helper function to create Python eventsAndreas Sandberg
Add a helper function, m5.event.create(), to create events from Python. This function takes a callable Python object (e.g., a function) as an argument and optionally a priority as a keyword argument. This function was accidentally dropped from the public API when switching to PyBind. Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3220 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-15style: fix line lengths and include orderingBrandon Potter
The style checker complains about line length and ordering for these files. This fix should make these two files kosher. Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d Reviewed-on: https://gem5-review.googlesource.com/3380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-05-15cpu: fix problem with forwarding and locked loadAlec Roelke
If a (regular) store is followed closely enough by a locked load that overlaps, the LSQ will forward the store's data to the locked load and never tell the cache about the locked load. As a result, the cache will not lock the address and all future store-conditional requests on that address will fail. This patch fixes that by preventing forwarding if the memory request is a locked load and adding another case to the LSQ forwarding logic that delays the locked load request if a store in the LSQ contains all or part of the data that is requested. [Merge second and last if blocks because their bodies are the same.] Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841 Reviewed-on: https://gem5-review.googlesource.com/2400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-15arm, dev: stub out GIC distributor interrupt groupsCurtis Dunham
We don't implement the GICD_IGROUPRn registers, which is allowed, but to be correct, they should be RAZ/WI (read as zero, writes ignored). Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12base: Make the VNC server more resilient.Gabe Black
If the client does something bad, don't kill the whole simulation, just complain, drop the client and keep going. Change-Id: I824f2d121e2fe03cdf4323a25c192b68e0370acc Reviewed-on: https://gem5-review.googlesource.com/3200 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12misc: Make the remote GDB stub more resilient to bad connections.Gabe Black
Currently, if the remote gdb stub fails to read a byte from an incoming packet because the connection has been dropped, the read call will return anyway and the calling code will have no way to know something bad happened. It might reattempt the read over and over again waiting for some particular byte, doomed to never make forward progress. This change modifies the remote GDB code so that if a read or write call fails, it will instead detach from the debugger and continue. Before this change, When simulating a port scan, ie connecting to the debugger port and then immediately dropping the connection using this command: nc -v -n -z -w 1 127.0.0.1 7000 gem5 would enter the previously described death spiral. After it, gem5 detaches from the bad connection and resumes execution. Subsequently attaching with gdb was successful. This code is written in a C centric style, and would benefit from some refactoring. Change-Id: Ie3c0bb35b9cfe3671d0f731e3907548bae0d292f Reviewed-on: https://gem5-review.googlesource.com/3180 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12syscall_emul: Fix undefined macro behaviorAndreas Sandberg
Clang's UBSAN implementation complains about macros that expand to expressions that contain 'defined'. Explicitly set the various feature macros to 1 or 0 to avoid this issue. Change-Id: Iba239dacfe526c43ab9c5da5183a350fc4fdc57d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3241
2017-05-12arm: Remove unused DumpStatsPCEventF class in FreeBSD systemAndreas Sandberg
The DumpStatsPCEventF is declared but lacks an implementation. This confuses RTTI in clang. Remove this class since it is clearly not needed. Change-Id: Ib95f09f2ba8593f8d0e072b96afd5f8a9ed31070 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3240 Reviewed-by: B.A. Zeeb <baz21@cam.ac.uk>
2017-05-10scons: Use the generalized switching headers on the GPU ISA.Gabe Black
Now that the switching header implementation has been generalized, there's no need to have two nearly identical implementations for the two different groups of headers. Change-Id: Ie7c24fcddbc672ac5ca2d69bfc35696f42c55580 Reviewed-on: https://gem5-review.googlesource.com/2984 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-10scons: arch: Generalize the switching header code.Gabe Black
Factor out the ISA ness of the switching header generating function. Also turn it into a SCons builder which builds a single header, and a wrapping method which uses the builder on a group of header files which all target the same subdirectory. Change-Id: I87705f97b6ebd9baebd4ebcfea19cc1218a64ad0 Reviewed-on: https://gem5-review.googlesource.com/2983 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09misc: Add the --listener-loopback-only command line option.Gabe Black
This option invokes the Listener::loopbackOnly() static function which will make the port listeners bind to the loopback device exclusively and ignore connections on other devices. That prevents external agents like port scanners from disrupting simulations with spurious connections. Change-Id: I46b22165046792a6f970826c109bdbce7db25c84 Reviewed-on: https://gem5-review.googlesource.com/3082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09misc: Expose the listener loopbackOnly function to python.Gabe Black
Change-Id: Ibb405af54a46a93706a6f476b5314491e84be0c8 Reviewed-on: https://gem5-review.googlesource.com/3081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09base: Teach the socket listeners how to bind to the loopback.Gabe Black
The loopback device will allow access to various services like remote GDB debugging, connecting to the terminal, etc., without letting external agents like port scanners connect and disrupting the simulation. Change-Id: I76dccbf152fa278ae9f342b25f7e345a1329fbe4 Reviewed-on: https://gem5-review.googlesource.com/3080 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09python: Fix debug flag listing regressionAndreas Sandberg
The PyBind11 changes slightly modified gem5's internal debug interfaces. The corresponding change to the public API went missing before the new bindings were merged. This change updates the Python glue to use the new interface. Change-Id: I3ecca5a3f6c35b99d55126d697371124f81a12dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-09arm: Enable m5ops by default for VExpress_GEM5_V1Andreas Sandberg
Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part of the CS5 address range in the RS1/RS2 memory map. Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2965
2017-05-09arm: Add support for memory-mapped m5opsAndreas Sandberg
Add support for a memory mapped m5op interface. When enabled, the TLB intercepts accesses in the 64KiB region designated by the ArmTLB.m5ops_base parameter. An access to this range maps to a specific m5op call. The upper 8 bits of the offset into the range denote the m5op function to call and the lower 8 bits denote the subfunction. Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2964
2017-05-09kvm, arm: Fix incorrect PSTATE syncAndreas Sandberg
The state transfer code wasn't reading back PSTATE correctly from the CPU prior to updating the thread context and was incorreclty writing the register as a 32-bit value when updating KVM. Correctly read back the state before updating gem5's view of PSTATE and cast the value to a uint64_t. Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2963 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-05-08scons: Get rid of the PHONY_BASE construction variable.Gabe Black
The value of that variable can be computed more directly and more locally to where it's consumed. Change-Id: I5ca1f732a34e22d4dae2aeb6ee7fc8adebe1caa0 Reviewed-on: https://gem5-review.googlesource.com/2981 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-08scons: Replace str(foo.get_contents()) with foo.get_text_contents().Gabe Black
For Value() nodes, the get_contents() method and the get_text_contents() method are just aliases to the same thing, both of which return a value which has already been converted using str(). The str() which was included explicitly in the SConscript was redundant, except that it showed that the value from get_contents was being treated as a string. To avoid the redundancy but to still leave a hint to the value's type, this change converts those bits of code to use get_text_contents() and removes the str(). Change-Id: I8f7da9b652f749e741b553c9a0e2248ae15ec3ca Reviewed-on: https://gem5-review.googlesource.com/3084 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-08scons: Make env['USE_PYTHON'] a source for createEnumStrings.Gabe Black
That clues scons in to the fact that the contents of the target of that function depends on the value of that construction variable. Change-Id: I803322ea1a178152da3d95dffffe20acd4271c88 Reviewed-on: https://gem5-review.googlesource.com/3083 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-05syscall_emul: Argument retrieval bug fixAlexandru Dutu
This commit fixes a stack-buffer underflow by fixing the way the array is indexed. Change-Id: I44400e2b99a2f8e1f48f673cd110b9dcd6480a72 Reviewed-on: https://gem5-review.googlesource.com/3040 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-05-03scons: Merge reading test SConscripts into makeEnv.Gabe Black
We're already visiting each of the environments, there's no reason to track them all and then set up test SConscripts on a second pass. Change-Id: I2d1166f58ac907e874d6ad5de7bd53ff7ad645f8 Reviewed-on: https://gem5-review.googlesource.com/2980 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-02python: Remove SWIGAndreas Sandberg
Remove SWIG-specific Python code. Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2922 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2017-05-02base, sim, dev: Remove SWIGAndreas Sandberg
Remove SWIG guards and SWIG-specific C++ code. Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2921 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
Use the PyBind11 wrapping infrastructure instead of SWIG to generate wrappers for functionality that needs to be exported to Python. This has several benefits: * PyBind11 can be redistributed with gem5, which means that we have full control of the version used. This avoid a large number of hard-to-debug SWIG issues we have seen in the past. * PyBind11 doesn't rely on a custom C++ parser, instead it relies on wrappers being explicitly declared in C++. The leads to slightly more boiler-plate code in manually created wrappers, but doesn't doesn't increase the overall code size. A big benefit is that this avoids strange compilation errors when SWIG doesn't understand modern language features. * Unlike SWIG, there is no risk that the wrapper code incorporates incorrect type casts (this has happened on numerous occasions in the past) since these will result in compile-time errors. As a part of this change, the mechanism to define exported methods has been redesigned slightly. New methods can be exported either by declaring them in the SimObject declaration and decorating them with the cxxMethod decorator or by adding an instance of PyBindMethod/PyBindProperty to the cxx_exports class variable. The decorator has the added benefit of making it possible to add a docstring and naming the method's parameters. The new wrappers have the following known issues: * Global events can't be memory managed correctly. This was the case in SWIG as well. Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2231 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves PĂ©neau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-01scons: Remove the SPAWN hack added earlier.Gabe Black
A previous change forced scons to spawn child processes by exec-ing it directly rather than going through the shell because the command line length would be too long for the shell to handle. Now that incremental linking should keep the command line lengths more under control, that change should no longer be necessary. Change-Id: I9e82a62083afd1414324a7fd697bd6d4b76367ae Reviewed-on: https://gem5-review.googlesource.com/2947 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-01scons: Group Source-s based on what SConscript included them.Gabe Black
The groups won't be perfectly balanced or optimally planned, but this requires no thought and breaks the object files down into a reasonable number of reasonably sized groups. Change-Id: I6542fc807aaf356a9be751093f68e2e29f0b1586 Reviewed-on: https://gem5-review.googlesource.com/2946 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-01scons: Put Source objects in groups and partially link them.Gabe Black
The groups will be linked together into intermediate partially linked object files. Right now the hierarchy is assumed to be flat, but with some effort it could be extended to allow truly hierarchical linking. Change-Id: I77b77710554e5f05e8b00720a0170afaf4afac2d Reviewed-on: https://gem5-review.googlesource.com/2945 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-01arch-sparc: Fix wrong indentation causing warnings for gcc 6Nikos Nikoleris
Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-01dev: Add ATA command used in recent Linux kernelsJason Lowe-Power
Add a case for the ATA command ATAPI_IDENTIFY_DEVICE. This avoids the panic: Unsupported ATA command when booting a recent Linux kernel. This was tested on 4.8.13. Change-Id: Ib297a2c02da0730d8698c59801254dd0f5ee9f7f Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/2863 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2017-04-18x86: fixed branching() computation for branch uopsSanti Galan
When a branch micro-op belongs to a flow and the micro-op does not change the nPC and just updates the nuPC (like a 'rep movs' flow), branching() function always returns not-taken no matter actual micro-branch outcome. Provided fix adds to the equation nuPC attribute checking since these kind of branch micro-op only updates that pointer. This issue has been found while debugging the performance of a copy-loop implemented with memcopy function. Without the fix, 'rep movss' internal micro-branch was always predicted as not-taken causing an squash event after every branch micro-branch execution. Using the provided test, branch mispredition went from 1922 without the fix to 7. Change-Id: I1bcbefae26aef47e3135817ef99b53d0ea0a98fa
2017-04-14scons: When spawning the linker process, don't involve the shell.Gabe Black
The command line can be too long, causing bash to choke. This means we can't use any shell syntax like shell variables or redirection when linking, but that should be easy to avoid. Change-Id: Ie6c8ecab337cef6bd3c7e403346ced06f46f0993 Reviewed-on: https://gem5-review.googlesource.com/2780 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Steve Reinhardt <stever@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11power: Allow global stats in power equationsStephan Diestelhorst
Allow global stats such as sim_seconds in power equations to make it possible to convert from event stats to rate stats. Change-Id: I429abe0ffadc0dbd162eb39e0897143be472ef65 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-08power: Clarify the unit used for the power equations (W)Stephan Diestelhorst
Change-Id: Iab5070fc9b666fcb5b49b0e2b99a4a1605b3b721 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-04-06power: Add a voltage variable to power expressionsAndreas Sandberg
There is currently no good way of extracting the current operating voltage in MathExprPowerModels. This change adds a magic variable, 'voltage', that can be referenced from such expressions to get the current operating voltage. Change-Id: Ice3c9a4a221921a542de5da52f83f3f88862d246 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2662 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-06power: Add error checking to MathExprPowerModelAndreas Sandberg
MathExprPower model currently doesn't print any useful error messages if an expression fails to evaluate. To add insult to injury, the model only detects a failure when dumping stats and not at initialization. This change adds a verification step in startup() that ensures that all of the referenced stats actually exist. Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05ruby: Fix MOESI_CMP_directory for new DMA status changes.Javier Cano-Cano
Multiple outstanding DMA requests introduced new DMA states that didn't be considered into slicc code. This patch implements the missed DMA state changes on MOESI_CMP_directory protocol. Change-Id: I700d441d76556b7e77e0d507904af6ec6ba59cc2 Signed-off-by: Michael LeBeane <michael.lebeane@amd.com> Reviewed-on: https://gem5-review.googlesource.com/2380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: add remote gdb supportAlec Roelke
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
Previously, if a memory operation referenced an address that caused the data to wrap around to the beginning of the memory (such as -1 or 0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and gem5 would crash. This patch fixes that by checking for such a case in RISC-V's TLB code and returning a fault from translateData if that would happen. Because RISC-V does support unaligned memory accesses, no checking is performed to make sure that an access doesn't cross a cache line. [Update creation of page table fault to use make_shared.] [Add comment explaining the change and assertion that the memory request isn't zero size.] Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410 Reviewed-on: https://gem5-review.googlesource.com/2345 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: add basic support for GICC_BPR registerCurtis Dunham
The Binary Point Register (BPR) specifies which bits belong to the group priority field (which are used for preemption) and which to the subpriority field (which are ignored for preemption). Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2443 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handlingCurtis Dunham
The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: refactor packet processing in Pl390 GICCurtis Dunham
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2441 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
Instructions that use the coprocessor interface check the current program status to determine whether the current context has the priviledges to read from/write to the coprocessor. Some modes allow the execution of coprocessor instructions, some others do not allow it, while some other modes are unexpected (e.g., executing an AArch32 instruction while being in an AArch64 mode). Previously we would unconditionally trigger a panic if we were in an unexpected mode. This change removes the panic and replaces it with an Undefined Instruction fault that triggers if and when a coprocessor instruction commits in an unexpected mode. This allows speculative coprocessor instructions from unexpected modes to execute but prevents them from gettting committed. Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>