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2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
The size of the store entry in the LSQ is used to indicate a fault in the execution of the store. At the same time, a store that is predicated false will also have 0 size in the corresponding store queue entry. This changeset ensures that we check if the store was predicated false before checking the size field. This way we avoid printing stores as faulting when they are only predicated false. Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris
The O3CPU allows stores to commit before they are completed and as soon as they enter the store queue. This is the reason why stores are verified by the the checker CPU, separately, once they complete and after they are sent to the memory. Store conditionals, on the other hand, have an additional writeback stage in the pipeline as they return their result to a register, similarly to loads. This is the reason why they do not commit before they receive a response from the memory. This allows store conditionals to be verified by the checker CPU as soon as they commit in the same way as all other non-store insturctions. At the same time, the presense of a checker CPU should not require changes to way we handle instructions. This change removes explicit calls to: * incorrectly set the extra data of the request to 0 (a subsequent call to completeAcc already does this without making any ISA assumptions about the return value of the failed store conditional) * complete failing store conditionals Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
mremapFunc(...) did not respect Process::mmapGrowsDown(). This resulted in an attempt to remap into an already allocated region and a panic in FuncPageTable::allocate(...). This behavior can be observed in 435.gromacs. Change-Id: Ib3ad33816126c76506d69679bdcefa7a98ef69f9 Reviewed-on: https://gem5-review.googlesource.com/4700 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
MOV Rd,Cd is MR encoded but the control register is operand 2 not operand 1 hence this needs to be MODRM_REG not MODRM_RM. While MOV Cd,Rd is RM encoded registers are also swapped, so it also needs to be MODRM_REG as well (as it already correctly is). This fixes incorrect UD2 reportings leading to invalid traps reported in O3 on X86 FS introduced with 4e939a7 . Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8 Reviewed-on: https://gem5-review.googlesource.com/4861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
Make the traceData panic for Vectors a warn_once. It's a pity it's not implemented but it's not a reason to abort the simulation entirely. Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df Reviewed-on: https://gem5-review.googlesource.com/4860 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
FreeBSD before the early 11 development is expecting a char * for stack.ss_sp rather than the standards compliant void *. Catch that case and allow gem5 to compile on old FreeBSD versions. Change-Id: Ic0ae560b52bfe5b3905ae87df791d349e053ec97 Reviewed-on: https://gem5-review.googlesource.com/4660 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-26util: Make dot_writer ignore NULL simobjects.Gabe Black
Also centralize the code which iterates over the parameters of a simnode's children, and remove a copy/paste block of code in the DVFS block of code. Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d Reviewed-on: https://gem5-review.googlesource.com/4849 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26dev: Make the IDE controller handle NULL simobject pointers.Gabe Black
Only panic if there are disks which would actually be connected to it beyond its limit. Also skip past disks which are set to NULL. This is useful since it lets you set up disks on different ports of the controller instead of filling them contiguously. Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7 Reviewed-on: https://gem5-review.googlesource.com/4848 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-26sim: Add a get_config_as_dict to the NullSimObject class.Gabe Black
Change-Id: I1ba6f6b196b7dfa790d1baaa23640bb3ed73f450 Reviewed-on: https://gem5-review.googlesource.com/4847 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-26sim: Don't add the NULL SimObject as a child of other SimObjects.Gabe Black
Change-Id: Ibdc48af8e5a461077f75d781cfd8191586c54115 Reviewed-on: https://gem5-review.googlesource.com/4846 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Give the NullSimObject singleton a _name.Gabe Black
The name is 'Null', and is what __str__ returns. Change-Id: I113f52496f5e9133b8d03206289b719fda003582 Reviewed-on: https://gem5-review.googlesource.com/4845 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a NullSimObject.descendants function.Gabe Black
Null simobjects don't have any descendants. Change-Id: Ia43a99056709f422c9c817c017912d23d689fb1e Reviewed-on: https://gem5-review.googlesource.com/4844 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a clear_parent function to NullSimObject.Gabe Black
Change-Id: I3842176f147997105fcc62aaf9cb93b9896708be Reviewed-on: https://gem5-review.googlesource.com/4843 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Check the SimObjectVector.has_parent function to use the "any" function.Gabe Black
The existing code was essentially doing the same thing, but in a more roundabout and obscure way. One difference between the two versions is that I believe this will stop as soon as it encounters an element without a parent, where the original version would call has_parent() on all the elements regardless. Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695 Reviewed-on: https://gem5-review.googlesource.com/4842 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Only consider non-NULL elements in SimObjectVector.has_parent.Gabe Black
NullSimObject doesn't have a has_parent function, and it's not clear what its return value should be if one were added. The appropriate value seems to depend on why some other bit of code is checking if there's a parent in the first place. In SimObjectVector, the has_parent function is checking whether all of its elements have a parent. In this particular case, the most reasonable thing to do seems to be to just skip those elements. Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8 Reviewed-on: https://gem5-review.googlesource.com/4841 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-26sim: Add a set_parent to NullSimObject which does nothing.Gabe Black
This lets attempts to set_parent on NullSimObject fall away harmlessly without having to add a bunch of checks whenever set_parent is called. Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11 Reviewed-on: https://gem5-review.googlesource.com/4840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-09-25mem: Fill the new packet ID fields with master IDs when tracing packets.Gabe Black
This will let somebody consuming the memory packet trace make sense out of the master IDs passed along with individual accesses. Change-Id: I621d915f218728066ce95e6fc81f36d14ae7e597 Reviewed-on: https://gem5-review.googlesource.com/4800 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-09-25mem: Add a "map" of packet IDs to strings in probe traces.Gabe Black
This map is intended to map from request MasterIDs to master names. It could be used to map to arbitrary strings in other situations, however. The original idea to store this information was to add a new message type which would store one ID and the string associated with it. This change stores the IDs in the header instead so that they'll be easy to find and all available before the packet data. One downside of this approach is that it won't be possible to add new master ID strings as they come up during a trace. If that becomes an issue, the two approaches could be combined and messages could be added which would augment the map in the header. Also worth mentioning is that the proto2 version of the protobuf description language does not support the "map" field type, and the protoc compiler on my workstation doesn't support proto3. Because that's such an appropriate representation for this data, the map is represented in an equivalent format described in the proto3 documentation. Change-Id: I137c8611c33d9ce6589e196d50c8638c1d88750c Reviewed-on: https://gem5-review.googlesource.com/4782 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-09-25mem: Trace the request master ID in the MemTraceProbe.Gabe Black
There's a spot for it in the packet trace protobuf, so we should fill it with something. Change-Id: I784feb3f668e1b20d67b6ef98d012bcf59b7bd40 Reviewed-on: https://soc-sim-internal-review.googlesource.com/3483 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-on: https://gem5-review.googlesource.com/4781 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-09-25mem: Record the request master ID in the PacketInfo structure.Gabe Black
That can be recorded in a packet trace. Change-Id: I3813ab4ea5aadeb40b355ff01f10e8ecab2bb790 Reviewed-on: https://soc-sim-internal-review.googlesource.com/3482 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-on: https://gem5-review.googlesource.com/4780 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-09-25dev, virtio: Improvements to diod process handlingAnouk Van Laer
* When dispatching multiple gem5 simulations at once, they race for the socket id, resulting in a panic when calling 'bind'. To avoid this problem, the socket id is now created before the diod process is created. In case of a race, a panic is called in the gem5 process, whereas before the panic was called in the diod process where it didn't have any effect. * In some cases killing the diod process in terminateDiod() using only SIGTERM failed, so a call using SIGKILL is added. Change-Id: Ie10741e10af52c8d255210cd4bfe0e5d761485d3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-21alpha: Move some initialization logic from loadState into unserialize.Gabe Black
The primary difference between loadState and unserialize, at least when eventually using the default SimObject implementation of loadState, is that unserialize is called only if there's a corresponding section in the checkpoint being restored. In this particular case, the AlphaProcess class calls the generic Process unserialize function, and that does other critical initialization like set up the processes page table. If the unserialize function isn't called, other serious problems would break the simulation anyway. This removes the final custom implementation of loadState. Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6 Reviewed-on: https://gem5-review.googlesource.com/4741 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-21sim: Stop using loadState in the Root SimObject.Gabe Black
The primary difference between using loadState and letting the default implementation of loadState call unserialize is that whether or not that code is called is dependent on that object being associated with a section in the checkpoint file being unserialized. Since there's always a "root" object, there should always be a section for it in the checkpoint and those should be equivalent. This removes one custom implementation of the loadState function. Change-Id: Ia674ccc18e141f38746e22ccfddc21475b1a0731 Reviewed-on: https://gem5-review.googlesource.com/4740 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-20kvm: arm: Get rid of functions which just wrap the subclasses version.Gabe Black
The MuxingKvmGic class defined a few functions related to checkpointing which did nothing other than call the underlying Pl390 implementation. These are unnecessary in general, and are particularly unnecessary for the loadState function which is a very lightly used part of the checkpointing interface. It's not actually defined in Pl390 either, and falls through to the underlying implementation. Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff Reviewed-on: https://gem5-review.googlesource.com/4760 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-11stats: Move the swpipl function into the Alpha kernel stats.Gabe Black
This stat is only incremented by Alpha. Also move the _hwrei into the Alpha stats object since it's the class that actually sets up and maintains that value and it probably should have been there all along. Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0 Reviewed-on: https://gem5-review.googlesource.com/4601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
The kernel stat mechanism should really be refactored and moved somewhere else, but in the mean time there's some old cruft that can be cleared away. Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86 Reviewed-on: https://gem5-review.googlesource.com/4600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-09-06cpu: Fix bi-mode branch predictor thresholdsRico Amslinger
When different sizes were set for the choice and global saturation counter (e.g. ex5_big), the threshold calculation used the wrong size. Thus the branch predictor always predicted "not taken" for choice > global. Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110 Reviewed-on: https://gem5-review.googlesource.com/4560 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-09-01cpu-minor: Fix for addr range coverage calculationPau Cabre
Coverage was wrongly set to PartialAddrRangeCoverage in the case of disjoint adjacent ranges Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4640 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Only increment SW PMU counters on writes to PMSWINCJose Marinho
When writing a bitmask of counters to PMSWINC, the PMU currently increments the corresponding counters regardless of what they are configured to count. According to the ARM ARM (D5.10.4), counters should only be updated if they have been configured to count software events (event type 0). Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4285 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30arch-arm: Add missing override keywords in fault.hhAndreas Sandberg
Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4284 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-08-30arch-x86: Add missing override in the X86 TLBAndreas Sandberg
Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4283 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
Recent gcc versions complain about a missing VecDisabled not having an explicit FaultVals instantiation. Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4282 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4281 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-30python: Make GlobalExitEvent.getCode() return an intAndreas Sandberg
PyBind normally casts integers returned from the C to long in Python. This is normally fine since long in most cases behaves just like an int. However, when passing the return value from getcode() to sys.exit, unexpected behavior ensues. Due to the way the function is defined, any type other than int (with the exception of None) will be treated as an error and be equivalent to sys.exit(1). Since we frequently use the sys.exit(event.getCode()) pattern, we need to ensure that the function returns an integer. This change adds an explicit type conversion to a Python integer in the wrapper code. Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4280 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com>
2017-08-30cpu-o3: fix data pkt initialization for split loadMatthias Hille
When a split load hits a memory region where IPRs are mapped, the Writebackevent which is scheduled for that was carrying a data packet that was not correctly initialized which caused an assertion to fire when the Writeback event is processed. Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f Signed-off-by: Matthias Hille <matthiashille8@gmail.com> Reported-by: Matthias Hille <matthiashille8@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/4620 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
The condition is whether the control register index is valid. Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64 Reviewed-on: https://gem5-review.googlesource.com/4581 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
A condition can be specified which will tell the decoder whether to return the instruction being requested, or, if the condition fails, UD2. Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd Reviewed-on: https://gem5-review.googlesource.com/4580 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-12dev: Fix an IDE error check.Gabe Black
The error message says an IDE controller can support at most 4 disks, but the check would fail if there were more than 3 disks. Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9 Reviewed-on: https://gem5-review.googlesource.com/4460 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-08-08mem-cache: Delete squashed HWPrefetchesPau Cabre
Request and Packet for squashed HWPrefetches were not deleted Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4340 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-08-02base: Give more information when setting up asynchronous IO fails.Gabe Black
When asynchronous IO fails, gem5 currently just says it failed and quits, and doesn't give any more information about which step failed, or what specifically about it failed. This change adds two helpers which will attempt the fcntl, check for error conditions, and in the event of a failure, include a message describing the error code and what the arguments to fcntl were. Change-Id: I316478172ab2aefd3788279dbc12744791385cd5 Reviewed-on: https://gem5-review.googlesource.com/4320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4263 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
Use named constants from a shared header instead of magic values when handling pseudo ops. Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4262 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
ISA devices typically run in the device event queue. Previously, we assumed that devices would perform their own EQ migrations as needed. This isn't ideal since it means we have different conventions for IO devices and ISA devices. Switch to doing migrations in the KVM CPU instead to make the behavior consistent. Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4288 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01kvm: Add a helper method to access device event queuesAndreas Sandberg
The VM's event queue is normally used for devices in multi-core KVM mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access this queue. This makes the intention of code migrating to device event queues clearer. Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01cpu, kvm: Fix deadlock issue when resuming a drained systemAndreas Sandberg
The KVM CPU sometimes needs to access devices when drain() is called. This typically happens on ARM when synchronizing devices that use the system register interface. When called from drain(), the event queue isn't locked since drain is called from the outside when the simulator isn't servicing any events. In such cases, performing a migration to the device's queue will unlock a mutex that isn't locked. This typically results in a deadlock when resuming the system since the lock will be in an undefined state. Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4286 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3965
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
The introduction of a new vector register class broke rename in the O3 CPU due to an unhandled register class in DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the necessary handling to avoid a panic when the vector register file is used. Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
Checkpointing a system with out-of-order CPUs might get stuck if one of the CPUs has been put to sleep. The quiesce instruction cannot get drained hence checkpointing never finishes. This commit resolves that by activating all suspended thread contexts when draining the system. Change-Id: I817ab1672b4ead777bd8e12a0445829481c46fdc Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3970 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
This fixes the function call to clone in syscall_emul.hh where the x86 version should be called before the base implementation of clone. Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3902 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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