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AgeCommit message (Expand)Author
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-04-04IDE: Support x86, Alpha, and ARM use of the IDE controller.Ali Saidi
2011-04-04ARM: Fix checkpointing case where PL111 is powered off.Ali Saidi
2011-04-04ARM: Remove debugging warn that was accidently left in.Ali Saidi
2011-04-04ARM: Fix multiplication error in udelayAli Saidi
2011-04-01hammer: fixed dma uniproc errorBrad Beckmann
2011-03-31CacheMemory: add allocateVoid() that is == allocate() but no return value.Lisa Hsu
2011-03-31Ruby: Simplify SLICC and Entry/TBE handling.Lisa Hsu
2011-03-31Ruby: Add new object called WireBuffer to mimic a Wire.Lisa Hsu
2011-03-31Ruby: have the rubytester pass contextId to Ruby.Lisa Hsu
2011-03-31Ruby: enable multiple sequencers in one controller.Lisa Hsu
2011-03-31Ruby: pass Packet->Req->contextId() to Ruby.Lisa Hsu
2011-03-31Ruby: Bug in SLICC forgot semicolon at end of code.Lisa Hsu
2011-03-29sim: typecast Tick to UTick for eventQ assertKorey Sewell
2011-03-29Power: Fix compilation.Gabe Black
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-24Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.Gabe Black
2011-03-24Arm: Get rid of the unused copyStringArray32 method from Arm process classes.Gabe Black
2011-03-24ISA parser: Set up op_src_decl and op_dest_decl for pc operands.Gabe Black
2011-03-22This patch fixes a build error in networktest.cc that occurs with gcc4.2Tushar Krishna
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
2011-03-21This patch makes garnet use the info about active and inactive vnets during a...Tushar Krishna
2011-03-21fix garnet fleible pipelineTushar Krishna
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
2011-03-20SLICC: Remove WakeUp* import calls from ast/__init__.pyNilay Vaish
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19Ruby: dma retry fixBrad Beckmann
2011-03-19RubyPort: minor fixes to trace flag and dprintfsBrad Beckmann
2011-03-19ruby: added useful dma progress dprintfBrad Beckmann
2011-03-19slicc: improved invalid transition messageBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
2011-03-18swig: get rid of m5.internal.random module (swig/random.i)Steve Reinhardt
2011-03-18base: disable FastAlloc in debug builds by defaultSteve Reinhardt
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
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