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2007-01-03Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2006-12-30Fix up previous commit to proper logic.Kevin Lim
src/cpu/o3/commit_impl.hh: Oops, changed the logic a little bit. Fix it up to how it used to be. --HG-- extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29FormattingNathan Binkert
--HG-- extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-28Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some ↵Gabe Black
debug output out of ifdefs. --HG-- extra : convert_revision : 29d0969e2d3e809aac32262ba20907e6e4ef1a42
2006-12-28Phased out DelaySlotInfo.Gabe Black
--HG-- extra : convert_revision : ab48db10caf38137300da63078aa9360f46b9631
2006-12-28Some fixes for decode stage branches without delay slots. This will need ↵Gabe Black
some work to be compatible with delay slots too. Also changed some direct variable uses to use an accessor function. --HG-- extra : convert_revision : b291292600e9d3e7e4a8255daf54342b736c7e35
2006-12-28Make sure the value of PC is actually updated now that the instruction ↵Gabe Black
target isn't set explicitly. --HG-- extra : convert_revision : 4c00a219ac1d82abea78e4e8d70f529a435fdfe2
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
--HG-- extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28Fixed NumMiscArchRegs. This is still a magic number, and it should be set ↵Gabe Black
automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti. --HG-- extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-27Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27Bug fixes in the TLBAli Saidi
Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27Compare legion and m5 tlbs for differencesAli Saidi
Only print faults instructions that aren't traps or faulting loads src/cpu/exetrace.cc: Compare the legion and m5 tlbs and printout any differences Only show differences if the instruction isn't a trap and isn't a memory operation that changes the trap level (a fault) src/cpu/m5legion_interface.h: update the m5<->legion interface to add tlb data --HG-- extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
--HG-- extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27No need to use NULL, just use 0Nathan Binkert
The result of operator= cannot be an l-value --HG-- extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-26Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.Kevin Lim
--HG-- extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
2006-12-24Make sure that all of the bits in the result are setNathan Binkert
to some value. --HG-- extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24remove some output formatting stuff that we don't useNathan Binkert
--HG-- extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-21Fix copyrightNathan Binkert
--HG-- extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
m5.internal.event.create(). It takes a python object and a Tick and calls process() when the Tick occurs. --HG-- extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
2006-12-21styleNathan Binkert
--HG-- extra : convert_revision : 6bbaaa88a608081eebf706ff30293f38729415aa
2006-12-21Stub for SE mode gdb support for MIPS.Gabe Black
--HG-- extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
--HG-- extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
src/python/swig/init.cc so that it's not as easy to forget about it when you add a new swig module. --HG-- extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
Also don't call (*activeThreads).end() over and over. Just call activeThreads->end() once and save the result. Make sure we always check that there are elements in the list before we grab the first one. --HG-- extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
2006-12-20Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : c1724538f27091e16ca495c8fdf2df06f55f7668
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
--HG-- extra : convert_revision : 1e946d9b1e1def36f9b8a73986dabf1b77096327
2006-12-20Fixes to get MIPS_SE to compile.Gabe Black
--HG-- extra : convert_revision : d173f212841341e436e9a38dcd3006d27886c1b8
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-20Initial work to make remote gdb available in SE mode. This is completely ↵Gabe Black
untested. --HG-- extra : convert_revision : 3ad9a3368961d5e9e71f702da84ffe293fe8adc8
2006-12-20Make sure the "stack_min" variable is page aligned.Gabe Black
--HG-- extra : convert_revision : e78c53778de83bdb2eca13d98d418b17b386ab29
2006-12-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : 4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
2006-12-19Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fa8ce7149973245a73bb562b9378db13be647a14
2006-12-19fix twinx loads a little bitAli Saidi
bugfixes and demap implementation in tlb ignore some more differencs for one cycle src/arch/sparc/isa/formats/mem/blockmem.isa: twinx has 2 micro-ops src/arch/sparc/isa/formats/mem/util.isa: fix the fault check for twinx src/arch/sparc/tlb.cc: tlb bugfixes and write demapping code src/cpu/exetrace.cc: don't halt on a couple more instruction (ldx, stx) when things differ beacuse of the way tlb faults are handled in legion. --HG-- extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
don't regenerate address from block in cache so that tags can turn around and use address to look up block again. --HG-- extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
--HG-- rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
--HG-- extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-18Fix a place where the wrong width parameter was used, and set the nextNPC ↵Gabe Black
correctly on memory squashes. --HG-- extra : convert_revision : 7914a48ea953607c48f93984e3b043098f0d7c62
2006-12-18Make sure you only handle branch delay slots specially when there actually ↵Gabe Black
was a branch. --HG-- extra : convert_revision : ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
2006-12-18Fixing the extended twin format to go with the new isa parser interface.Gabe Black
--HG-- extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
2006-12-18Fix unittest compilesNathan Binkert
--HG-- extra : convert_revision : 1163437081e1f1eab3f4512d04317dc94a673b9b
2006-12-18cast chars to int when we want to print integers so we get a numberNathan Binkert
instead of a character --HG-- extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-18Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmemGabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3 --HG-- extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
2006-12-18move the twinx loads to the correct opcode and add asis 0x24 and 0x27Ali Saidi
Make the TLB ok to translate QUAD_LDD src/arch/sparc/isa/decoder.isa: move the twinx loads to the correct opcode. src/arch/sparc/tlb.cc: Make QUAD_LDD asi ok to execute --HG-- extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-17Minor cleanup of new snippet/subst code.Steve Reinhardt
--HG-- extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/operands.isa: Hand Merge --HG-- extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
2006-12-17Compilation fixes.Gabe Black
--HG-- extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17Added in the extended twin load formatGabe Black
src/arch/sparc/isa/decoder.isa: Added the extended twin load instructions src/arch/sparc/isa/formats/mem/blockmem.isa: Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later. --HG-- extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17Started removing "CodeBlock" objects from the mips isa description.Gabe Black
--HG-- extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 10:40:08 +0000