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AgeCommit message (Expand)Author
2010-08-20ruby: Updated MOESI_hammer L2 latency behaviorBrad Beckmann
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
2010-08-20ruby: fix ruby llsc support to sync sc outcomesBrad Beckmann
2010-08-20ruby: Fixed L2 cache miss profilingBrad Beckmann
2010-08-20ruby: Added bcast msg profiling to hammer and tokenBrad Beckmann
2010-08-20ruby: Added consolidated network msg statsBrad Beckmann
2010-08-20ruby: Reincarnated the responding machine profilingBrad Beckmann
2010-08-20MOESI_CMP_token: Fixed dma persistent lockdown bugsBrad Beckmann
2010-08-20memtest: Memtester support for DMABrad Beckmann
2010-08-20ruby: Added ruby_request_type ostream def to libruby.hhBrad Beckmann
2010-08-20slicc: Consolidated the protocol stats printingBrad Beckmann
2010-08-20config: Added the topology description to m5 config.iniBrad Beckmann
2010-08-20ruby: Fixed printout when Sequencer detects a deadlockBrad Beckmann
2010-08-20MESI_CMP_directory: bug fix for old PUTX requestsBrad Beckmann
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17x86: minor checkpointing bug fixesSteve Reinhardt
2010-08-17sim: revamp unserialization procedureSteve Reinhardt
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
2010-08-17sim: clean up child handlingSteve Reinhardt
2010-08-17sim: move iterating over SimObjects into Python.Steve Reinhardt
2010-08-17sim: fail on implicit creation of orphans via portsSteve Reinhardt
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
2010-08-17bus: clean up default responder code.Steve Reinhardt
2010-08-14Inorder: Fix compilation of m5.fast.Gabe Black
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13InOrder: Clean up some DPRINTFs that print data sent to/from the cache.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
2010-07-22Power: The condition register should be set or cleared upon a system callTimothy M. Jones
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22Syscall: Don't close the simulator's standard file descriptors.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
2010-07-22Power: Provide a utility function to copy registers from one thread contextTimothy M. Jones
2010-07-21stats: unify the two stats distribution type betterNathan Binkert
2010-07-21stats: cleanup a few small problems in statsNathan Binkert
2010-07-21python: add a sorted dictionary classNathan Binkert
2010-07-21python: Add mechanism to override code compiled into the exectuableNathan Binkert
2010-07-21Fix x86 XCHG macro-op to use locked micro-ops for all memory accessesTushar Krishna
2010-07-17SimObject: transparently forward Python attribute refs to C++.Steve Reinhardt
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction f...Gabe Black
2010-07-13ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.Gabe Black
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
2010-07-08garnet: Added topology print function to Garnet printStatsBrad Beckmann
2010-07-08NetworkMessage copy constructor fixTushar Krishna
2010-07-05checkpointing: another small overload fixSteve Reinhardt
2010-07-05sim: allow SimObject subclasses to define classmethodsSteve Reinhardt
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
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