summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2013-06-18x86: Add helper functions to access rflagsAndreas Sandberg
2013-06-18x86: Fix the flag handling code in FABS and FCHSAndreas Sandberg
2013-06-11kvm: Add more VM statsAndreas Sandberg
2013-06-11kvm: Separate host frequency from simulated CPU frequencyAndreas Sandberg
2013-06-11kvm: Don't handle IO and execute in the same tickAndreas Sandberg
2013-06-11kvm: Maintain a local instruction counter and update totalNumInstsAndreas Sandberg
2013-06-11x86: Fix bug when copying TSC on CPU handoverAndreas Sandberg
2013-06-11sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...)Andreas Sandberg
2013-06-11cpu: Add support for scheduling multiple inst/load stop eventsAndreas Sandberg
2013-06-09ruby: remove several unused variables in ProfilerNilay Vaish
2013-06-09ruby: remove periodic event from ProfilerNilay Vaish
2013-06-09ruby: stats: use gem5's stats for cache and memory controllersNilay Vaish
2013-06-09ruby: remove undefined functions in Address classNilay Vaish
2013-06-09stats: allow printing vectors on a single lineNilay Vaish
2013-06-04dev: Clarify why updates are delayed when the MC14818 is activatedAndreas Sandberg
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-06-03base: Make the Python module loader PEP302 compliantAndreas Sandberg
2013-06-03kvm: Allow architectures to override the cycle accounting mechanismAndreas Sandberg
2013-06-03kvm: Add handling of EAGAIN when creating timersAndreas Sandberg
2013-06-03sim: Add debug output when executing pseudo-instructionsAndreas Sandberg
2013-06-03kvm: Add a call to thread->startup() in startup()Andreas Sandberg
2013-06-03dev: Add support for disabling ticking and the divider in MC146818Andreas Sandberg
2013-06-03dev: Clean up MC146818 register (A & B) handlingAndreas Sandberg
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-05-30cpu: Prune the stale TraceCPUAndreas Hansson
2013-05-30cpu: Check that minimum TrafficGen period is less than max periodSascha Bischoff
2013-05-30cpu: Fix bug when reading in TrafficGen state transitionsSascha Bischoff
2013-05-30cpu: Add request elasticity to the traffic generatorAndreas Hansson
2013-05-30cpu: Block traffic generator when requests have to retryAndreas Hansson
2013-05-30cpu: Move traffic generator sending out of generator statesAndreas Hansson
2013-05-30cpu: Fold together the StateGraph and the TrafficGenAndreas Hansson
2013-05-30mem: Make returning snoop responses occupy response layerAndreas Hansson
2013-05-30mem: Make the buses multi layeredAndreas Hansson
2013-05-30mem: Separate the two snoop response cases in the busAndreas Hansson
2013-05-30mem: Tidy up a few variables in the busAndreas Hansson
2013-05-30mem: Add basic stats to the busesUri Wiener
2013-05-30mem: Use unordered set in bus request trackingAndreas Hansson
2013-05-30mem: Check for waiting state in bus drainingAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Adapt the LPDDR2 to match a single x32 channelAndreas Hansson
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
2013-05-30base: Avoid size limitation on protobuf coded streamsAndreas Hansson
2013-05-30cpu: Make hash struct instead of class to please clangAndreas Hansson
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21x86: Squash outstanding walks when instructions are squashed.Gedare Bloom
2013-05-21x86: mark instructions for being function call/returnNilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 00:51:25 +0000