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2011-02-13X86: Don't read in dest regs if all bits are replaced.Gabe Black
In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register.
2011-02-13X86: On a bad microopc, return a microop that returns a fault that panics.Gabe Black
This way a bad micropc will have to get all the way to commit before killing the simulation. This accounts for misspeculated branches.
2011-02-13X86: Define fault objects to carry debug messages.Gabe Black
These faults can panic/warn/warn_once, etc., instead of instructions doing that themselves directly. That way, instructions can be speculatively executed, and only if they're actually going to commit will their fault be invoked and the panic, etc., happen.
2011-02-13X86: Only reset npc to reflect instruction length once.Gabe Black
When redirecting fetch to handle branches, the npc of the current pc state needs to be left alone. This change makes the pc state record whether or not the npc already reflects a real value by making it keep track of the current instruction size, or if no size has been set.
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-12Ruby: Reorder Cache Lookup in Protocol FilesNilay Vaish
The patch changes the order in which L1 dcache and icache are looked up when a request comes in. Earlier, if a request came in for instruction fetch, the dcache was looked up before the icache, to correctly handle self-modifying code. But, in the common case, dcache is going to report a miss and the subsequent icache lookup is going to report a hit. Given the invariant - caches under the same controller keep track of disjoint sets of cache blocks, we can move the icache lookup before the dcache lookup. In case of a hit in the icache, using our invariant, we know that the dcache would have reported a miss. In case of a miss in the icache, we know that icache would have missed even if the dcache was looked up before looking up the icache. Effectively, we are doing the same thing as before, though in the common case, we expect reduction in the number of lookups. This was empirically confirmed for MOESI hammer. The ratio lookups to access requests is now about 1.1 to 1.
2011-02-12inorder: clean up the old way of inst. schedulingKorey Sewell
remove remnants of old way of instruction scheduling which dynamically allocated a new resource schedule for every instruction
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
allow the pipeline and resources to use the cached instruction schedule and resource sked iterator
2011-02-12inorder: define iterator for resource schedulesKorey Sewell
resource skeds are divided into two parts: front end (all insts) and back end (inst. specific) each of those are implemented as separate lists, so this iterator wraps around the traditional list iterator so that an instruction can walk it's schedule but seamlessly transfer from front end to back end when necessary
2011-02-12inorder: stage scheduler for front/back end schedule creationKorey Sewell
add a stage scheduler class to replace InstStage in pipeline_traits.cc use that class to define a default front-end, resource schedule that all instructions will follow. This will also replace the back end schedule in pipeline_traits.cc. The reason for adding this is so that we can cache instruction schedules in the future instead of calling the same function over/over again as well as constantly dynamically alllocating memory on every instruction to try to figure out it's schedule
2011-02-12inorder: cache instruction schedulesKorey Sewell
first step in a optimization to not dynamically allocate an instruction schedule for every instruction but rather used cached schedules
2011-02-12inorder: comments for resource sked classKorey Sewell
2011-02-12inorder: remove unused fileKorey Sewell
inst_buffer file isn't used , so remove it
2011-02-12inorder: remove unused isa opsKorey Sewell
pass/fail ops were used for testing but arent part of isa
2011-02-11VNC/ARM: Use VNC server and add support to boot into X11Ali Saidi
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-11Serialization: Allow serialization of stl listsAli Saidi
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
When a table walk is initiated by the fetch stage, the CPU can potentially move to the idle state and never wake up. The fetch stage must call cpu->wakeCPU() when a translation completes (in finishTranslation()).
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode.
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk ↵Ali Saidi
occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs.
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-11ARM: Fix timer calculations.Ali Saidi
The timer calculations were a bit off so time would run faster than it otherwise should
2011-02-11Timesync: Make sure timesync event is setup after curTick is unserializedAli Saidi
Setup initial timesync event in initState or loadState so that curTick has been updated to the new value, otherwise the event is scheduled in the past.
2011-02-09ruby: removed duplicate make response callBrad Beckmann
2011-02-08MESI CMP: Unset TBE pointer in L2 cache controllerNilay Vaish
The TBE pointer in the MESI CMP implementation was not being set to NULL when the TBE is deallocated. This resulted in segmentation fault on testing the protocol when the ProtocolTrace was switched on.
2011-02-07X86: Obey the wp bit of CR0.Tim Harris
If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode.
2011-02-07X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.Tim Harris
During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address)
2011-02-07X86: Fix JMP_FAR_I to unpack a far pointer correctly.Tim Harris
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode.
2011-02-07X86: Read the LDT/GDT at CPL0 when executing an iret.Tim Harris
During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated).
2011-02-07Orion: Replace printf() with fatal()Nilay Vaish
The code for Orion 2.0 makes use of printf() at several places where there as an error in configuration of the model. These have been replaced with fatal().
2011-02-07ruby: add stdio header in SRAM.hhKorey Sewell
missing header file caused RUBY_FS to not compile
2011-02-07X86: Fix compiling vtophys.ccGabe Black
2011-02-06ruby: support to stallAndWait the mandatory queueBrad Beckmann
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06ruby: minor fix to deadlock panic messageBrad Beckmann
2011-02-06garnet: Split network power in ruby.statsJoel Hestness
Split out dynamic and static power numbers for printing to ruby.stats
2011-02-06MOESI_hammer: fixed dir bug counting received acksBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06MOESI_CMP_token: removed unused message fieldsTushar Krishna
2011-02-06mem: Added support for Null data packetBrad Beckmann
The packet now identifies whether static or dynamic data has been allocated and is used by Ruby to determine whehter to copy the data pointer into the ruby request. Subsequently, Ruby can be told not to update phys memory when receiving packets.
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06dev: fixed bugs to extend interrupt capability beyond 15 coresBrad Beckmann
2011-02-06x86: Timing support for pagetable walkerJoel Hestness
Move page table walker state to its own object type, and make the walker instantiate state for each outstanding walk. By storing the states in a queue, the walker is able to handle multiple outstanding timing requests. Note that functional walks use separate state elements.
2011-02-06TimingSimpleCPU: split data sender state fixJoel Hestness
In sendSplitData, keep a pointer to the senderState that may be updated after the call to handle*Packet. This way, if the receiver updates the packet senderState, it can still be accessed in sendSplitData.
2011-02-06ruby: Fix RubyPort to properly handle retrysBrad Beckmann
2011-02-06Ruby: Fix to return cache block size to CPU for split data transfersJoel Hestness
2011-02-06Ruby: Add support for locked memory accesses in X86_FSJoel Hestness
2011-02-06Ruby: Update the Ruby request type names for LL/SCJoel Hestness
2011-02-06ruby: Assert for x86 misaligned accessBrad Beckmann
This patch ensures only aligned access are passed to ruby and includes a fix to the DPRINTF address print.
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann