Age | Commit message (Collapse) | Author |
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handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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Oops!
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this as well.
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squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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implementations from using doubles to using concatenated singles.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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test the stub code for instructions.
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parser as a unit.
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unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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size than the architected one. Also fixed some asserts.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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and added some comments to main.isa
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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x86-centric stuff.
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seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
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rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
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sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.
1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.
In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.
src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
Implemented polymorphic microops and changed around the microcode assembler syntax.
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substitution.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : 7181d8c2ee673322372484cf288a94ebd91b5265
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functions.
src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
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into zeep.pool:/z/saidi/work/m5.newmem
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deletePortRefs() is called on it with that port as a parameter.
In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather
than creating a new one each time.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/cache_impl.hh:
only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if
a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc)
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definitions to make figuring out what's what a little easier:
MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
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capitalized. Before, it had the first letter capitalized but all the others lower case
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and a real hash function.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
fixed twin memory operations.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
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