| Age | Commit message (Collapse) | Author |
|---|
|
This fixes the function call to clone in syscall_emul.hh where
the x86 version should be called before the base implementation
of clone.
Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
To make it clearer what the register indices are for the semantically
meaningful registers defined by src/arch/riscv/registers.hh, the
constants that were defined using other constants were changed to use
the literal values of those constants. This also removes the need to
use the M5_VAR_USED attribute.
Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61
Reviewed-on: https://gem5-review.googlesource.com/4080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
When both the C and C++ versions are visible, the compiler will complain that
it doesn't know which one to use. By specifying the std namespace, it will
know to use the C++ version.
Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22
Reviewed-on: https://gem5-review.googlesource.com/4060
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.
Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Reviewed-on: https://gem5-review.googlesource.com/4040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
The interswitch is broken prior to this commit, with LDM to the PC
ignoring the switch.
Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Reviewed-on: https://gem5-review.googlesource.com/3520
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3930
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3929
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3928
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3927
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I897b6162a827216b7bad74d955c0e50e06a5a3ec
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3926
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Change-Id: Ifafdcf4692d58a17f90e66ff8de8fa3e146c34bb
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3924
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3923
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Change-Id: Ic1332b8e8ba0afacbe591c80f4d06afbf5f04bd9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3922
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
|
|
Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I09570e569efe55f5502bc201e03456738999e714
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3920
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.
Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3963
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
|
|
This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C. Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).
[Update diassembly generation for new RegId type.]
[Rebase onto master.]
Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.
[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]
Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2,
and GICD_PIDR3.
Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3961
|
|
ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0
Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3960
|
|
The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.
Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3967
|
|
OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called
Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Reported-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3966
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
|
|
With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.
Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3968
|
|
Change tickCycles numCycles stat name to totalTickCycles os as not to
clash with the name of the tickCycles stat of the same class.
Declared the params passed to the TickedObject constructer as const.
Call ClockedObject::regStats() from the TickedObject::regStats to
ensure the correct initialization of the base class (ClockedObject)
stats
Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3964
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining. The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.
Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.
Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.
Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3660
|
|
Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.
Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.
Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
|
|
This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.
Nathanael's idea, Rekai's implementation.
Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2704
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The Result union used to collect the result of an instruction is now a
class of its own, with its constructor, and explicit casting methods for
cleanliness.
This is also a stepping stone to have vector registers, and instructions
that produce a vector register as output.
Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2703
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
With the hierarchical RegId there are a lot of functions that are
redundant now.
The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.
Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702
|
|
Mimic the changes done on the architectural register indexes on the
physical register indexes. This is specific to the O3 model. The
structure, called PhysRegId, contains a register class, a register
index and a flat register index. The flat register index is kept
because it is useful in some cases where the type of register is not
important (dependency graph and scoreboard for example). Instead
of directly using the structure, most of the code is working with
a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId
objects are stored in the regFile.
Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2701
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
|
|
The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'. The latter acts as a way to access the
backing store without architectural 'effects'. For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device. The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.
For Kvm execution, a delicate balance must be struck for the
timer device specifically. We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync. On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.
In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5. The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.
Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The timer device exposed via the ARM ISA, also known as the
"CP15 timer" due to its legacy coprocessor encodings, is
implemented by the GenericTimerISA class. During Kvm
execution, however, this functionality is directly emulated
by the hardware.
This commit subclasses the GenericTimer, which is (solely)
used by GenericTimerISA, to facilitate Kvm in much the same
way as the prior GIC changes: the gem5 model is used as the
backing store for state, so checkpointing and CPU switching
work correctly, but isn't used during Kvm execution.
The added indirection prevents the timer device from creating
events when we're just updating its state, but not actually
using it for simulation.
Change-Id: I427540d11ccf049c334afe318f575146aa888672
Reviewed-on: https://gem5-review.googlesource.com/3542
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Having timer events stored in checkpoints complicates Kvm
execution. We change the timer behavior so that it always
deschedules any pending events on a drain() and recreates
them on a drainResume(), thus they will never appear in
checkpoints henceforth. This pattern of behavior makes
it simpler to handle Kvm execution, where the hardware
performs the timer function directly.
Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f
Reviewed-on: https://gem5-review.googlesource.com/3541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The check was nearly completely generic anyway,
with the exception of the Kvm CPU type.
This will make it easier for other parts of the
codebase to do similar checks.
Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Reviewed-on: https://gem5-review.googlesource.com/3540
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3901
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I6a3a57e3067c247bd6ce6f01ac9459883f4aae2c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3880
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
|
32bit and 64bit Linux have different arguments passed to the
__switch_to() function that gem5 hooks into in order to collect context
switch statistics. 64bit Linux provides the task_struct pointer to the
next task that will be switched to, which means we don't have to look
up the task_struct from thread_info as we do in 32bit ARM Linux.
This patch adds a second set of accessors to ThreadInfo to extract
details such as the pid, tgid, task name, etc., directly from a
task_struct. The existing accessors maintain their existing behavior by
first looking up the task_struct and then calling these new accessors.
A 64-bit variant of the DumpStatsPCEvent class is added that uses these
new accessors to get the task details for the context switch dumps
directly from the task_struct passed to __switch_to().
Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d
Reviewed-on: https://gem5-review.googlesource.com/2640
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
To prevent this warning from printing for *every* simulation, this patch
adds a check to only print the warning if we are not at the beginning of
simulation.
Change-Id: I7f6154f0ca26bef6280f909f799aa1c7936b624a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/3840
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
|
|
Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3747
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3746
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s
event names to not properly match the rank they were generated by. This
could occur if the public rank member is modified after the Rank's
construction. A patch would mean refactoring Rank and `DRAMCtrl`b to
privatize many of the members of Rank behind getters.
Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3745
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
|
In order to replicate the same `name()` output with `PacketQueue`, subclasses
using EventFunctionWrapper must initialize PacketQueue with their own name so
the sendEvent holds the name of the subclass.
Change-Id: Ib091e118bab8858192e1d1370d61def42958ec29
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3744
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
