summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04misc: Move the ExitLogger class definition into misc.ccGabe Black
This class isn't referred to outside of misc.hh, and isn't necessarily useful outside of the particular logging setup implemented in misc.cc. The Logger class itself is different since it provides a generic interface that can be used with different logging schemes. Change-Id: Ibae926fea039d9e3d75a43d97348bc4a3c5d555e Reviewed-on: https://gem5-review.googlesource.com/6225 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Remove trietest's dependence on cprintf.Gabe Black
Dumping the structure of the tries being constructed was useful for debugging when the trie data structure was being developed, but the output can't be automatically verified easily, and what's considered correct depends on the specific implementation of the trie itself. To make some of the earlier tests more meaningful, additional lookups were added which verified that the correct values were returned when the nodes of the trie were in particular arrangements. Change-Id: Ib464ad1804d13fe40882da2190d7bf452da83818 Reviewed-on: https://gem5-review.googlesource.com/6223 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Add a ptr helper function trietest.Gabe Black
This function casts an integer constant into a uint32_t * to make the actual test lines a bit less verbose. Change-Id: I9307dfd3d5861ddb9c0f6dcf4b28c846004f0a8d Reviewed-on: https://gem5-review.googlesource.com/6222 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Get rid of the bitvectest unit test.Gabe Black
This test doesn't really test anything other than the STL vector implementation. Change-Id: I1b932640b1be4fb92a44d314d0b51a94a6a324a2 Reviewed-on: https://gem5-review.googlesource.com/6221 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
Arm security extension introduced register banking between secure and non-secure mode. This has been removed in armv8 using AArch64 in EL3, where the decoded register is by default the non-secure version. Using non-secure register infos(flags) was preventing secure execution to access the register with the MRC/MCR at EL1. The patch updates the following banked registers' flags so that their non-secure version can be accessed in secure mode: MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0, MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR, MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR, MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1, MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR, MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL, MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL For those registers the following permission bits have been set: MISCREG_PRI_S_RD MISCREG_PRI_S_WR Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6201 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
Replace manual creation of masks for sign extension of immediates with the sext<N> function. Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c Reviewed-on: https://gem5-review.googlesource.com/6182 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
This patch makes mem.isa conform to style guidelines better by removing spaces around the "ea_code" argument default value assignment of the Load format. Change-Id: I1c62b99de3617a3734b128b00fb421773e021317 Reviewed-on: https://gem5-review.googlesource.com/6181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
Some of the files in earlier patches rearranging instruction definitions were missing copyright and license information. This patch adds them. Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87 Reviewed-on: https://gem5-review.googlesource.com/6183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-29cpu: Don't override ISA if provided by userAndreas Sandberg
The BaseCPU.createThreads() method currently overrides the BaseCPU.isa parameter. This is sometimes undesirable. Change the behavior so that the default value for the isa parameter is the empty list and teach createThreads() to only override the ISA if none has been specified. Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-29cpu-minor: Add missing instruction statsDavid Guillen Fandos
Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Updated to use IsVector instruction flag. ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5732 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Reviewed-on: https://gem5-review.googlesource.com/6023 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
All of the O3 vector stats added by 'arch: ISA parser additions of vector registers' are currently missing their stat initializers. Add the missing stat initialization to InstructionQueue::regStats. Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6101 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-28arch-arm: Add haveEL pseudocode functionGiacomo Travaglini
This patch introduces the ARM pseudocode haveEL function into gem5. Change-Id: I0d96070959e8e13773eb7fa9964894ec0ff2cac2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6162 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28arch-arm: Add assertions when extracting an ArmSystem from a TCGiacomo Travaglini
We sometimes need to cast the System pointer stored in a ThreadContext to an ArmSystem pointer to query global system setting. Add an assertion to make sure that the cast resulted in a valid pointer. Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6161 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28tests: Move the bituniontest to be alongside the bitunion header.Gabe Black
Change-Id: I7c1a49c41672a1108fcf67c5505b0441f90588ef Reviewed-on: https://gem5-review.googlesource.com/6142 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28scons: Build GTests in the directory they're declared.Gabe Black
This will let us move unit tests into the directory of the code they're testing. Change-Id: I611582eb00a06a848f3ce7da89f64e42660cb844 Reviewed-on: https://gem5-review.googlesource.com/6141 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28tests: Reimplement the bituniontest as a googletest.Gabe Black
The implementation is very similar to the old test structurally, and should test all the same things. Change-Id: I58f1559d0943f2494ef06ee1d7ee5314a3852a8c Reviewed-on: https://gem5-review.googlesource.com/6085 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28scons: Add in a new type of unit test called GTest.Gabe Black
This type of unit test is almost the same as UnitTest, except that it builds in the googletest library with the appropriate flags, and it also omits all the gem5 object files by default. Change-Id: I230db7ede563a73a9da0ebeed44aca389f724465 Reviewed-on: https://gem5-review.googlesource.com/6084 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28scons: Minor cleanup of how partial linking is handled in makeEnv.Gabe Black
Git rid of the unused partial_objs variable, and change append to extend since the result of builders is a list of nodes and not individual nodes, even if there's only one target. Change-Id: Ie51225d3ea699eb7da18199ac3bf3e868e3994a6 Reviewed-on: https://gem5-review.googlesource.com/5985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
This patch creates an "insts" directory in src/arch/riscv to store static portions of instruction definitions that aren't part of the code generated by the ISA description. It serves as a starting point for future patches to simplify the ISA description. Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa Reviewed-on: https://gem5-review.googlesource.com/6021 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-27tests: Build the input file into the initest unit test.Gabe Black
This breaks an external dependency and makes the expected command line conform to the other unit tests. Also get rid of some ancient tests which test adding to the ini's contents based on command line arguments. This test still needs to be modified so that it actually checks whether what happened was correct. Change-Id: I2c9ea9fa79781bceb5cd3d1419870924e8bbd45f Reviewed-on: https://gem5-review.googlesource.com/6081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27scons: Break make_obj into make_static and make_shared functions.Gabe Black
The make_obj function took a boolean value which just selected which of the two lines it in would actually do something. This change breaks it into two lambdas, make_static and make_shared, which just do whichever line would have been requested, making the funciton name more self descriptive and getting rid of the generally unnamed and opaque boolean argument. Change-Id: I457e40034b7e7f5a3e7294a8e1f15bbd42e0720e Reviewed-on: https://gem5-review.googlesource.com/5984 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27scons: Remove the extra_deps option from the helper function make_obj.Gabe Black
This had only one use, and made the function more complicated than it needed to be. Change-Id: I22147a0c1239b457c577a6a24b423065e539833b Reviewed-on: https://gem5-review.googlesource.com/5983 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27scons: Get rid of a flag which makes Werror optional.Gabe Black
This flag wasn't being used. Also move the Werror code to the SConstruct now that it's being applied universally. Change-Id: I18b00d4b41bc1add9271ca299c020c14970a6926 Reviewed-on: https://gem5-review.googlesource.com/5982 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27scons: Move some compiler flag setting code to the SConstruct.Gabe Black
These settings are invariant, so there's no reason to apply them over and over again for the child environments used for various build products. Change-Id: Icb4053105e4f1c43008f2422ba30c7206b7ff365 Reviewed-on: https://gem5-review.googlesource.com/5981 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27scons: Get rid of SourceFile's done function.Gabe Black
This function doesn't seem to be used by anything. A similar one off mechanism exists for SimObjects which is we might also be able to get rid of. Change-Id: I65038c3495fa69cf94042dc78f09876d5e9a557f Reviewed-on: https://gem5-review.googlesource.com/5841 Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
Tags are just arbitrary strings which are attached to source files which mark them as having some property. By default, all source files have the "gem5 lib" tag added to them which marks them as part of the gem5 library, the primary component of the gem5 binary but also a seperable component for use in, for example, system C. The tags can be completely overridden by setting the "tags" parameter on Source, etc., functions, and can be augmented by setting "add_tags" which are tags that will be added, or alternatively additional tags. It's possible to specify both, in which case the tags will be set to the union of tags and add_tags. add_tags is supposed to be a way to add extra tags to the default without actually overriding the default. Both tags and add_tags can be a list/tuple/etc of tags, or a single string which will be converted into a set internally. Other existing tags include: 1. "python" for files that need or are used with python and are excluded when the --without-python option is set 2. "main" for the file(s) which implement the gem5 binary's main function. 3. The name of a unit test to group its files together. 4. Tags which group source files for partial linking. By grouping the "tags" into a single parameter instead of taking all extra parameters as tags, the extra parameters can, in the future, be passed to the underlying scons environment. Also, the tags are either present or not. With guards, they could be present and True, present and False, or not present at all. Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2 Reviewed-on: https://gem5-review.googlesource.com/5822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-22tests: Resurrect initest input file(s).Gabe Black
Delete the current version of foo.ini which was modified, restore the previous version, and initest.ini. Preprocess initest.ini which includes foo.ini, and tidy up the resulting file. This file will (mostly) get the initest unit test to work. Some other cleanups are still necessary. Change-Id: I4e46abc73ac89f88177eec92f572452f63ba8019 Reviewed-on: https://gem5-review.googlesource.com/6041 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22tests: Fix the stats unit test.Gabe Black
This has been broken since February. The interface for opening initializing where the stats output should go was changed, but the test wasn't updated. Change-Id: I54bd8be15bf870352d5fcfad95ded28d87c7cc5a Reviewed-on: https://gem5-review.googlesource.com/6001 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-22arch-arm: Add support for the brk instructionAndreas Sandberg
Add support for software breakpoints as signalled by the aarch64 brk instruction. This introduces a new SoftwareBreakpoint fault. Change-Id: I93646c3298e09d7f7b0983108ba8937c7331297a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5721 Reviewed-by: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
2017-11-22arch-arm: HVC instruction undefined in secure EL1Giacomo Travaglini
Since EL2 is not available in secure mode, any HVC call from secure mode should be treated as undefined. This behaviour was implemented in aarch32 HVC but not in 64 bit version Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5921 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-22arch-riscv: Add missing system callsAlec Roelke
This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] [Remove spaces around default arguments of createSyscall for better style] [Switch from using a loose function to using SyscallDesc's new constructor] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Reviewed-on: https://gem5-review.googlesource.com/5322 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-22sim-se: Add default to SyscallDesc constructorAlec Roelke
This patch adds a default value of unimplementedFunc to SyscallDesc's constructor's second argument, which makes adding system call placeholders to SE mode cleaner. Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb Reviewed-on: https://gem5-review.googlesource.com/5501 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-11-22sparc: Move integer StaticInst base classes out of the ISA desc.Gabe Black
Change-Id: I24008c1e2a94ad8dc4cc13739214928eb846a496 Reviewed-on: https://gem5-review.googlesource.com/5483 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Move the mem base classes out of the ISA description.Gabe Black
Change-Id: Ifbeee464e2d7f872e192f065ad3494f52d274596 Reviewed-on: https://gem5-review.googlesource.com/5482 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Move the microop/macroop base classes out of the ISA desc.Gabe Black
These were just raw C++ classes. Change-Id: Id2101400d885c6938efb6b94f2949722cfbb94ae Reviewed-on: https://gem5-review.googlesource.com/5481 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Return debug faults from unimplemented instructions.Gabe Black
These had been marked as non-speculative so that their execute functions would only be called if the instruction should really be executed. Instead, we can return faults which will cause the same behavior when the instruction is committed and let the instruction execute as normal. Change-Id: I39fa5073e93399424144724b99bdc12070e42286 Reviewed-on: https://gem5-review.googlesource.com/5465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Pull the unimplemented formats out of the ISA description.Gabe Black
These are simple classes which don't need to be in the ISA description. Change-Id: Ia0bb45f50c4da2536855efcb3c17c7780b431332 Reviewed-on: https://gem5-review.googlesource.com/5464 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Pull the "Uknown" StaticInst class out of the ISA description.Gabe Black
The only thing the Unknown format does is return an instance of this class, so there's no reason to have it in the ISA description. Change-Id: I3f8187b1450a8622a974c030c0cb552b26f6b5f0 Reviewed-on: https://gem5-review.googlesource.com/5463 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Pull most of the Nop format out of the ISA description.Gabe Black
The Nop format mostly just made instructions that inherited from the Nop base class but with different mnemonics, so there doesn't need to be very much dynamic content. Change-Id: I1cf5e25ca8372f9b71f56d49756879c7545c9f6c Reviewed-on: https://gem5-review.googlesource.com/5462 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Pull more StaticInst base classes out of the ISA desc.Gabe Black
These are for the trap and branch instructions. Change-Id: Idedab6f3e6c6c954c1f8a36dae52976cf25ad394 Reviewed-on: https://gem5-review.googlesource.com/5461 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-22sparc: Pull flat static instruction classes out of the ISA.Gabe Black
These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-21arch-arm: ArmPMU refactorJose Marinho
Change the definition of PMU events in order to integrate events not cannot easily be represented by probe points. The software increment event is now defined as a special type with its separate implementation in pmu.cc and pmu.hh. Change-Id: I43874b9641bf38c54f6ba2c26386542b6a73e282 Signed-off-by: Jose Marinho <jose.marinho@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5764 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-21arch-arm: Do not increment PMU cycle event in WFI/WFEJose Marinho
Change-Id: I09531e9992e045254e5ee989dd11ccabbf84e4ce Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5763 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
Move the code responsible for performing the actual probe point notify into BaseCPU. Use BaseCPU activateContext and suspendContext to keep track of sleep cycles. Create a probe point (ppActiveCycles) that does not count cycles where the processor was asleep. Rename ppCycles to ppAllCycles to reflect its nature. Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5762 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-21sim: Fix need to save address space info during serialization.Austin Harris
This fixes a fatal already mapped error in FuncPageTable::allocate that occurs in some cases when restoring from a checkpoint. Change-Id: Ib726a69358118626663e42b7f14889b0d3a98de0 Reported-by: Ruohuang Zheng <zhengruohuang@gmail.com> Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/5901 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 21:21:46 +0000