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AgeCommit message (Expand)Author
2012-09-14scons: Restructure ccflags and ldflagsAndreas Hansson
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-11X86: make use of register predicationNilay Vaish
2012-09-11x86: Add a separate register for D flag bitNilay Vaish
2012-06-03ISA Parser: Allow predication of source and destination registersNilay Vaish
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
2012-09-10Mem: Allow serializing of more than INT_MAX bytesMarco Elver
2012-09-10NetBSD: Build on NetBSDPalle Lyckegaard
2012-09-10AddrRange: Remove the unused range_ops headerAndreas Hansson
2012-09-10Inet: Remove the SackRange and its useAndreas Hansson
2012-09-10Device: Bump PIO and PCI latencies to more reasonable valuesAndreas Hansson
2012-09-07sim: Update the SimObject documentationAndreas Sandberg
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07dev: Fix bifield definition in timer_cpulocal.hhAli Saidi
2012-09-07Igbe: Newer kernels seem to allow TSO headers and packet data to be in one descAli Saidi
2012-09-07sim: add validation to make sure there is memory where we're loading the kernelKrishnendra Nathella
2012-09-07loader: initialize all memory in the ObjectFile objects.Ali Saidi
2012-09-07ARM: Fix one of the timers used in the VExpress EMM platform.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness
2012-08-28Ruby: Correct DataBlock =operatorJason Power
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-28Port: Stricter port bind/unbind semanticsAndreas Hansson
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-08-28swig: Disable unused value warning with llvm 3.1 compilersAndreas Hansson
2012-08-27sim: fix overflow check in simulate because Tick is now unsignedAnthony Gutierrez
2012-08-27Ruby: remove README.debugging and Decommissioning_noteNilay Vaish
2012-08-27System: Remove redundant call to startupCPUNilay Vaish
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
2012-08-27Ruby Memory Vector: Allow more than 4GB of memoryNilay Vaish
2012-08-25MESI Protocol: Correct the virtual network in profile functionsNilay Vaish
2012-08-25MESI Coherence Protocol: Add copyright noticeNilay Vaish
2012-08-22DMA: Refactor the DMA device and align timing and atomicAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-21Device: Remove overloaded pio_latency parameterAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21PacketQueue: Allow queuing in the same tick as desired send tickAndreas Hansson
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