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Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.
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This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.
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be done.
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execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
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port.
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http://www.m5sim.org/flyspray/task/197
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
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where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
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Don't mark upstream MSHR as pending if downstream MSHR is already in service.
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standard switch and change some ifs to work with the default port since every port is now connected to something.
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to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
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test instructions.
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immediate where they should use a register.
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Alignment is done as it was for 32 bit processes.
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file descriptors are reopened and the file pointer is in the same
place as when the checkpoint occured.
Signed-off by: Ali Saidi
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