| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-08-23 | X86: Consolidate extra microop flags into one parameter. | Gabe Black | |
| This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. | |||
| 2010-08-23 | CPU: Make the constants for StaticInst flags visible outside the class. | Gabe Black | |
| 2010-08-23 | O3: Skipping mem-order violation check for uncachable loads. | Min Kyu Jeong | |
| Uncachable load is not executed until it reaches the head of the ROB, hence cannot cause one. | |||
| 2010-08-23 | ARM: Improve printing of uop disassembly. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Clean up flattening for SPSR adding | Min Kyu Jeong | |
| 2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ↵ | Gene Wu | |
| the TLB | |||
| 2010-08-23 | ARM: Don't write tracedata on writes, it might have been freed already. | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX init/complete acc methods | Gene Wu | |
| 2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
| 2010-08-23 | Devices: Allow a device to specify that a request is uncachable. | Gene Wu | |
| 2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu | |
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Get SCTLR TE bit from reset SCTLR | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-08-23 | CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag | Min Kyu Jeong | |
| 2010-08-23 | CPU: Make Exec trace to print predication result (if false) for memory ↵ | Min Kyu Jeong | |
| instructions | |||
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong | |
| Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR | |||
| 2010-08-23 | O3: Handle loads when the destination is the PC. | Min Kyu Jeong | |
| For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory | |||
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong | |
| THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. | |||
| 2010-08-23 | ARM: adding genMachineCheckFault() stub for ARM that doesn't panic | Min Kyu Jeong | |
| 2010-08-23 | ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵ | Gene Wu | |
| ARMv7 | |||
| 2010-08-23 | ARM: Temporary local variables can't conflict with isa parser operands. | Gene Wu | |
| PC is an operand, so we can't have a temp called PC | |||
| 2010-08-23 | ARM: Exclusive accesses must be double word aligned | Ali Saidi | |
| 2010-08-23 | ARM: Add some registers for big loads/stores to support neon. | Ali Saidi | |
| 2010-08-23 | ARM: Decode neon memory instructions. | Ali Saidi | |
| 2010-08-23 | ARM: Clean up the ISA desc portion of the ARM memory instructions. | Gabe Black | |
| 2010-08-23 | Loader: Don't insert symbols into the symbol table that begin wiht '$'. | Ali Saidi | |
| 2010-08-23 | ARM: We don't currently support ThumbEE exceptions, so don't report that we do | Ali Saidi | |
| 2010-08-23 | ARM: Change how the AMBA device ID checking is done to make it more generic | Ali Saidi | |
| 2010-08-23 | ARM: Add system for ARM/Linux and bootstrapping | Ali Saidi | |
| 2010-08-23 | ARM: Add I/O devices for booting linux | Ali Saidi | |
| --HG-- rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh | |||
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-08-23 | ARM: Fix an un-initialized variable bug | Ali Saidi | |
| 2010-08-23 | Loader: Use address mask provided to load*Symbols when loading the symbols ↵ | Ali Saidi | |
| from the symbol table. | |||
| 2010-08-23 | Loader: Make the load address mask be a parameter of the system rather than ↵ | Ali Saidi | |
| a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0. | |||
| 2010-08-23 | ARM: Finish the timing translation when taking a fault. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Use a stl queue for the table walker state | Dam Sunwoo | |
| 2010-08-23 | CPU: Set a default value when readBytes faults. | Ali Saidi | |
| This was being done in read(), but if readBytes was called directly it wouldn't happen. Also, instead of setting the memory blob being read to -1 which would (I believe) require using memset with -1 as a parameter, this now uses bzero. It's hoped that it's more specialized behavior will make it slightly faster. | |||
| 2010-08-23 | Compiler: Fixes for GCC 4.5. | Ali Saidi | |
| 2010-08-23 | BASE: Fix genrand to generate both 0s and 1s when max equals one. | Ali Saidi | |
| previously was only generating 0s. | |||
| 2010-08-23 | stats: Fix off-by-one error in distributions. | Ali Saidi | |
| bkt size isn't evenly divisible by max-min and it would round down, it's possible to sample a distribution and have no place to put the sample. When this case occured the simulator would assert. | |||
| 2010-08-22 | X86: Get rid of unused file arguments.hh. | Gabe Black | |
| 2010-08-22 | SPARC: Fix some style issues in utility.hh. | Gabe Black | |
| 2010-08-22 | X86: Get rid of the unused getAllocator on the python base microop class. | Gabe Black | |
| This function is always overridden, and doesn't actually have the right signature. | |||
| 2010-08-20 | ruby: Added merge GETS optimization to hammer | Brad Beckmann | |
| Added an optimization that merges multiple pending GETS requests into a single request to the owner node. | |||
| 2010-08-20 | ruby: Fixed minor bug in ruby test for setting the request type | Brad Beckmann | |
| 2010-08-20 | ruby: Stall and wait input messages instead of recycling | Brad Beckmann | |
| This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py | |||
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