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AgeCommit message (Expand)Author
2006-10-31Ports now have a pointer to the MemObject that owns it (can be NULL).Kevin Lim
2006-10-25Fix fixPacket functionality to calculate sizes properlyRon Dreslinski
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-24Add more traceflags for ethernetAli Saidi
2006-10-24Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
2006-10-23get rid of the "resume" step at the end of changeToTiming/Atomic because this...Lisa Hsu
2006-10-23make this parallel to the other cpu types so that resume works correctly.Lisa Hsu
2006-10-23Minor compile fix. Not sure why this is broken.Gabe Black
2006-10-23Move around more SPARC memory code, and make block memory operations work wit...Gabe Black
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-23Broke Load/Store instructions into microcode, and partially refactored memory...Gabe Black
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
2006-10-23Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <in...Gabe Black
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some minor...Gabe Black
2006-10-23Change the default constructors to take ExtMachInsts rather than regular Mach...Gabe Black
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
2006-10-22s/pktuest/request/ (all in comments)Steve Reinhardt
2006-10-22Add DPRINTF for non-timed quiesce.Steve Reinhardt
2006-10-21Small bug fixes for timing LL/SC. Better now butSteve Reinhardt
2006-10-21Add Quiesce trace flag to track CPU quiesce/wakeup events.Steve Reinhardt
2006-10-21Just give up if a store conditional misses completelySteve Reinhardt
2006-10-21Fix formatting that got screwed up when tabs were removed.Steve Reinhardt
2006-10-21Refactor coherence state table initialization.Steve Reinhardt
2006-10-21Tweak a few things for better page fault debugging.Steve Reinhardt
2006-10-21Missing caseNathan Binkert
2006-10-20Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-20Construct a correct value of PYTHONHOME from the interpreterNathan Binkert
2006-10-20Get rid of a variable put back by merge.Ron Dreslinski
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
2006-10-20Merge zizzer:/bk/newmemAli Saidi
2006-10-20still working on getting past initializationAli Saidi
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-19initialize end, clean up loopNathan Binkert
2006-10-19Fix compile of m5.fastNathan Binkert
2006-10-19Fix corner case on assertion.Ron Dreslinski
2006-10-19Fix memtester to use functional access, fix cache to work functionally now th...Ron Dreslinski
2006-10-19Small changes:Ron Dreslinski
2006-10-19Fixes to get single level uni-coherence to work.Ron Dreslinski
2006-10-19Merge zizzer:/bk/newmemRon Dreslinski
2006-10-19Always get the functional access from the highest level of cache first.Ron Dreslinski
2006-10-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-10-19Add "All" compund flag to enable all defined trace flags.Steve Reinhardt
2006-10-19Add new event priority for trace enable events soSteve Reinhardt
2006-10-19First cut at LL/SC support in caches (atomic mode only).Steve Reinhardt
2006-10-18Zeroed out the actual LSB in addition to moving it's original value the MSB.Gabe Black
2006-10-18Fixed up exetrace.cc to deal with microcode, and to made floating point regis...Gabe Black
2006-10-18Fixed a compiler error, disassembly output, and corrected the address calcula...Gabe Black
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