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src/arch/sparc/SConscript:
Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface.
src/arch/sparc/asi.hh:
Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions.
src/arch/sparc/asi.cc:
Implementation of some ASI utility functions.
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src/kern/linux/linux.hh:
src/kern/solaris/solaris.hh:
Some code cleanup. Uncommented some typedefs.
src/kern/tru64/tru64.hh:
Some code cleanup. Deleted an obsoleted function.
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src/SConscript:
add intel nic to sconscript
src/dev/pcidev.cc:
fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
Move config_latency into pci where it belogs
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various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
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into ewok.(none):/home/gblack/m5/newmem
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into zeep.pool:/z/saidi/work/m5.newmem.head
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configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops
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Includes support for printing readable VectorPort and Proxy names
(via __str__).
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Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
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and resulting recursive import trickiness.
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Some tweaking to deal with mutually recursive imports.
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rename : src/python/m5/config.py => src/python/m5/SimObject.py
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Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
src/python/m5/config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
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the live process
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into vm1.(none):/home/stever/bk/newmem-head
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
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allowing derived classes to be simplified.
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implementing faligndata more correctly.
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Verify that BAR sizes are powers of two.
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the framework. Doesn't work, but also doesn't break uni-processor systems.
Working on pulling out the changes in the cache so that it remains working.
src/mem/bus.cc:
Changes for multi-phase snoop
Some code for registering snoop ranges (a version that compiles and runs, but does nothing)
src/mem/bus.hh:
Changes for multi-phase snoop
src/mem/packet.hh:
Flag for multi-phase snoop
src/mem/port.hh:
Status for multi-phase snoop
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into ewok.(none):/home/gblack/m5/newmem
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Added in the filename parameter which is provided for the user space linker.
Fix the ordering and alignment of stack elements.
Made mmap start with the address it has been seen starting with "in the wild"
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