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Age
Commit message (
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Author
2013-06-24
ruby: remove the three files related to profiling
Nilay Vaish
2013-06-24
ruby: MessageBuffer: Remove unused m_size variable
Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-06-20
ruby: fix typo in MOESI_CMP_token protocol
Lena Olson
2013-06-18
ruby: Fix prefetching for MESI_CMP_Directory
Lena Olson
2013-06-18
ruby: fix slicc compiler to complain about duplicate symbols
Lena Olson
2013-06-18
ruby: restrict Address to being a type and not a variable name
Lena Olson
2013-06-18
x86: Add support for maintaining the x87 tag word
Andreas Sandberg
2013-06-18
x86: Fix loading of floating point constants
Andreas Sandberg
2013-06-18
x86: Initialize the MXCSR register
Andreas Sandberg
2013-06-18
x86: Make the boot state VMX compliant
Andreas Sandberg
2013-06-18
x86: Make fprem like the fprem on a real x87
Andreas Sandberg
2013-06-18
kvm: Use the address finalization code in the TLB
Andreas Sandberg
2013-06-18
x86: Add helper functions to access rflags
Andreas Sandberg
2013-06-18
x86: Fix the flag handling code in FABS and FCHS
Andreas Sandberg
2013-06-11
kvm: Add more VM stats
Andreas Sandberg
2013-06-11
kvm: Separate host frequency from simulated CPU frequency
Andreas Sandberg
2013-06-11
kvm: Don't handle IO and execute in the same tick
Andreas Sandberg
2013-06-11
kvm: Maintain a local instruction counter and update totalNumInsts
Andreas Sandberg
2013-06-11
x86: Fix bug when copying TSC on CPU handover
Andreas Sandberg
2013-06-11
sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...)
Andreas Sandberg
2013-06-11
cpu: Add support for scheduling multiple inst/load stop events
Andreas Sandberg
2013-06-09
ruby: remove several unused variables in Profiler
Nilay Vaish
2013-06-09
ruby: remove periodic event from Profiler
Nilay Vaish
2013-06-09
ruby: stats: use gem5's stats for cache and memory controllers
Nilay Vaish
2013-06-09
ruby: remove undefined functions in Address class
Nilay Vaish
2013-06-09
stats: allow printing vectors on a single line
Nilay Vaish
2013-06-04
dev: Clarify why updates are delayed when the MC14818 is activated
Andreas Sandberg
2013-06-03
arch: Create a method to finalize physical addresses
Andreas Sandberg
2013-06-03
base: Make the Python module loader PEP302 compliant
Andreas Sandberg
2013-06-03
kvm: Allow architectures to override the cycle accounting mechanism
Andreas Sandberg
2013-06-03
kvm: Add handling of EAGAIN when creating timers
Andreas Sandberg
2013-06-03
sim: Add debug output when executing pseudo-instructions
Andreas Sandberg
2013-06-03
kvm: Add a call to thread->startup() in startup()
Andreas Sandberg
2013-06-03
dev: Add support for disabling ticking and the divider in MC146818
Andreas Sandberg
2013-06-03
dev: Clean up MC146818 register (A & B) handling
Andreas Sandberg
2013-05-30
mem: More descriptive DRAM config names
Andreas Hansson
2013-05-30
mem: Add bytes per activate DRAM controller stat
Andreas Hansson
2013-05-30
mem: Add static latency to the DRAM controller
Andreas Hansson
2013-05-30
mem: Spring cleaning of MSHR and MSHRQueue
Andreas Hansson
2013-05-30
mem: Fix MSHR print format
Andreas Hansson
2013-05-30
cpu: Prune the stale TraceCPU
Andreas Hansson
2013-05-30
cpu: Check that minimum TrafficGen period is less than max period
Sascha Bischoff
2013-05-30
cpu: Fix bug when reading in TrafficGen state transitions
Sascha Bischoff
2013-05-30
cpu: Add request elasticity to the traffic generator
Andreas Hansson
2013-05-30
cpu: Block traffic generator when requests have to retry
Andreas Hansson
2013-05-30
cpu: Move traffic generator sending out of generator states
Andreas Hansson
2013-05-30
cpu: Fold together the StateGraph and the TrafficGen
Andreas Hansson
2013-05-30
mem: Make returning snoop responses occupy response layer
Andreas Hansson
2013-05-30
mem: Make the buses multi layered
Andreas Hansson
2013-05-30
mem: Separate the two snoop response cases in the bus
Andreas Hansson
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