gem5 - gem5

Age	Commit message (Expand)	Author
2017-11-27	scons: Get rid of a flag which makes Werror optional.	Gabe Black
2017-11-27	scons: Move some compiler flag setting code to the SConstruct.	Gabe Black
2017-11-27	scons: Get rid of SourceFile's done function.	Gabe Black
2017-11-27	scons: Switch from "guards" to "tags" on source files.	Gabe Black
2017-11-22	tests: Resurrect initest input file(s).	Gabe Black
2017-11-22	tests: Fix the stats unit test.	Gabe Black
2017-11-22	arch-arm: Add support for the brk instruction	Andreas Sandberg
2017-11-22	arch-arm: HVC instruction undefined in secure EL1	Giacomo Travaglini
2017-11-22	arch-riscv: Add missing system calls	Alec Roelke
2017-11-22	sim-se: Add default to SyscallDesc constructor	Alec Roelke
2017-11-22	sparc: Move integer StaticInst base classes out of the ISA desc.	Gabe Black
2017-11-22	sparc: Move the mem base classes out of the ISA description.	Gabe Black
2017-11-22	sparc: Move the microop/macroop base classes out of the ISA desc.	Gabe Black
2017-11-22	sparc: Return debug faults from unimplemented instructions.	Gabe Black
2017-11-22	sparc: Pull the unimplemented formats out of the ISA description.	Gabe Black
2017-11-22	sparc: Pull the "Uknown" StaticInst class out of the ISA description.	Gabe Black
2017-11-22	sparc: Pull most of the Nop format out of the ISA description.	Gabe Black
2017-11-22	sparc: Pull more StaticInst base classes out of the ISA desc.	Gabe Black
2017-11-22	sparc: Pull flat static instruction classes out of the ISA.	Gabe Black
2017-11-21	arch-arm: ArmPMU refactor	Jose Marinho
2017-11-21	arch-arm: Do not increment PMU cycle event in WFI/WFE	Jose Marinho
2017-11-21	cpu, cpu, sim: move Cycle probe update	Jose Marinho
2017-11-21	sim: Fix need to save address space info during serialization.	Austin Harris
2017-11-21	arch-arm: Fix MCR/MRC disassemble	Giacomo Travaglini
2017-11-21	arch-arm: Fix MSR/MRS disassemble	Giacomo Travaglini
2017-11-21	cpu-o3: Prevent cpu from suspending if it is already draining	Nikos Nikoleris
2017-11-20	arch-arm: Ensure counters keep events on checkpoint resume	Jose Marinho
2017-11-20	cpu: Make automatic transition to OFF optional	Jose Marinho
2017-11-20	pwr: Adds logic to enter power gating for the cpu model	Anouk Van Laer
2017-11-20	sparc: Pull StaticInst base classes out of the ISA description.	Gabe Black
2017-11-20	dev: Fix the SPARC and X86 platform devices.	Gabe Black
2017-11-19	tests: Fix compilation of cprinftest.	Gabe Black
2017-11-17	sim: Implement load_addr_mask auto-calculation	Geoffrey Blake
2017-11-16	sim: ScopedMigration does nothing if both eqs are the same	Tiago Muck
2017-11-16	ext, mem: Pull DRAMPower SHA 90d6290 and rebase	Radhika Jagtap
2017-11-16	pwr: Enable multiple power models per component	David Guillen Fandos
2017-11-16	arch, arm: Print value being ignored on DummyISA write	Sean McGoogan
2017-11-16	sim: Clocked object debug message updated for clarity	Tiago Muck
2017-11-16	sim: Add an option to load additional kernel objects	Andreas Sandberg
2017-11-15	arch-arm: Dsb instruction shouldn't flush the pipeline	Giacomo Travaglini
2017-11-15	arch-arm: Writes to DCCMVAC shouldn't flush pipeline	Giacomo Travaglini
2017-11-15	arch-arm: Removing FlushPipe fault, using SquashAfter	Giacomo Travaglini
2017-11-15	arm: Add support for armv8 CRC32 instructions	Giacomo Travaglini
2017-11-14	cpu, probe: Fix elastic trace register dependency	Radhika Jagtap
2017-11-13	config: Add an Energy param type.	Gabe Black
2017-11-13	config: Export the "Current" param type from m5.params.	Gabe Black
2017-11-13	util: Add a "toEnergy" function to the convert module.	Gabe Black
2017-11-13	config: Simplify the definitions of the Voltage and Current params.	Gabe Black
2017-11-13	arch-arm: Interface for the ArmStaticInst intWidth field	Giacomo Travaglini
2017-11-13	arch-arm: Corrected encoding for T32 HVC instruction	Giacomo Travaglini