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AgeCommit message (Expand)Author
2013-02-19scons: Unify the flags shared by gcc and clangAndreas Hansson
2013-02-19scons: Add warning delete with non-virtual destructorAndreas Hansson
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for missing field initializersAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-19base: Fix a bug in the address interleavingAndreas Hansson
2013-02-19mem: Ensure trace captures packet fields before forwardingAndreas Hansson
2013-02-15loader: add a flattened device tree blob (dtb) objectAnthony Gutierrez
2013-02-15arm: fix a page table walker issue where a page could be translated multiple ...Mrinmoy Ghosh
2013-02-15cpu: Document exec trace flagsAndreas Sandberg
2013-02-15dev: Use the correct return type for disk offsetsAndreas Sandberg
2013-02-15cpu: Avoid duplicate entries in tracking structures for writes to misc regsGeoffrey Blake
2013-02-15cpu: Fix rename mis-handling serializing instructions when resource constrainedGeoffrey Blake
2013-02-15ARM: Postpones creation of framebuffer output file until it is actually used.Chris Emmons
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2012-10-25arm: Don't export private GIC methodsAndreas Sandberg
2012-10-25arm: Create a GIC base class and make the PL390 derive from itAndreas Sandberg
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
2013-02-15ARM: Fix an issue with clang generating wrong code.Ali Saidi
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
2013-02-14Ruby: Fix compilation errors on gcc 4.7 and clang 3.2Andreas Hansson
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
2013-02-10ruby: enable multiple clock domainsNilay Vaish
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
2013-02-10ruby: replace Time with Cycles in garnet fixed and flexibleNilay Vaish
2013-02-10ruby: replace Time with Tick in replacement policy classesNilay Vaish
2013-02-10ruby: convert block size, memory size to unsignedNilay Vaish
2013-02-10ruby: replace Time with Cycles in MessageBufferNilay Vaish
2013-02-10ruby: replace Time with Cycles in Memory ControllerNilay Vaish
2013-02-10ruby: Replace Time with Cycles in SequencerMessageNilay Vaish
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