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AgeCommit message (Expand)Author
2015-12-07mem: Add instruction sequence number to requestRadhika Jagtap
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
2015-12-04sim: Get rid of the non-const serialize() methodAndreas Sandberg
2015-12-04arm, config: Automatically discover available platformsAndreas Sandberg
2015-12-04dev, arm: Disable R/B swap in HDLCD by defaultAndreas Sandberg
2015-12-04dev, arm: Split MCC and DCC subsystemsAndreas Sandberg
2015-12-04sim: Add support for generating back traces on errorsAndreas Sandberg
2015-12-03arm: Add support for automatic boot loader selectionAndreas Sandberg
2015-12-03dev, mips: Remove the unused MaltaPChip classAndreas Sandberg
2015-12-01config: Fix broken SimObject listingAndreas Sandberg
2015-11-24dev: Remove unnecessary header includeAndreas Sandberg
2015-11-25mem: Fix search-replace issues in DRAMPower wrapper licenseAndreas Hansson
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
2015-11-22arm, dev: Fix flash model serialization code typosGeoffrey Blake
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
2015-11-22arm: Fix fplib 128-bit shift operatorsNathanael Premillieu
2015-11-22cpu: Fix memory leak in traffic generatorAndreas Hansson
2015-11-20cpu: Enforce 1 interrupt controller per threadAndreas Sandberg
2015-11-16Merged changesets: 47e2adf7fb1a and b65d4e878ed2Nilay Vaish
2015-11-16x86: Invalidating TLB entry on page faultSwapnil Haria
2015-11-16x86: cpuid: add family to warn() messageBjoern A. Zeeb
2015-11-16x86: pagetable walker: fix typo in commentBjoern A. Zeeb
2015-11-16sparc: Make remote debugging with gdb workPalle Lyckegaard
2015-11-16o3: drop unused statistic wbPenalized and wbPenalizedRateNilay Vaish
2015-11-15arm: Add missing explicit overrides for classic cachesAndreas Sandberg
2015-07-20ruby: added stl vector of ints to be used by SLICCBrad Beckmann
2015-11-13slicc: fixes for the Address to Addr changeset (11025)Tony Gutierrez
2015-11-13ruby: add BoolVecJoe Gross
2015-07-20mem: add boolean to disable PacketQueue's size sanity checkBrad Beckmann
2015-11-11dev, arm: Initialized the iccrpr register in the GICAndreas Sandberg
2015-11-05dev: Add basic checkpoint support to VirtIO9PProxy deviceSascha Bischoff
2015-11-09dev: Remove unused header includesAndreas Sandberg
2015-11-09dev: Don't access the platform directly in PCI devicesAndreas Sandberg
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
2015-11-06mem: Add cache clusivityAndreas Hansson
2015-11-06mem: Avoid unnecessary snoops on writebacks and clean evictionsAli Jafri
2015-11-06mem: Order packet queue only on matching addressesAndreas Hansson
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
2015-11-06mem: Use the packet delays and do not just zero them outAndreas Hansson
2015-11-06mem: Align rules for sinking inhibited packets at the slaveAndreas Hansson
2015-11-06mem: Do not treat CleanEvict as a write operationAndreas Hansson
2015-11-06mem: Unify delayed packet deletionAndreas Hansson
2015-11-06misc: Appease clang static analyzerAndreas Hansson
2015-11-06mem: Check the XBar's port queues on functional snoopsAndreas Sandberg
2015-11-03mem: hmc: minor fixesErfan Azarkhish
2015-11-03mem: hmc: serial link modelErfan Azarkhish
2015-11-03mem: hmc: adds controllerErfan Azarkhish
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