summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
2011-03-21This patch makes garnet use the info about active and inactive vnets during ↵Tushar Krishna
allocation and power estimations etc
2011-03-21fix garnet fleible pipelineTushar Krishna
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
The tester code is in testers/networktest. The tester can be invoked by configs/example/ruby_network_test.py. A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-20SLICC: Remove WakeUp* import calls from ast/__init__.pyNilay Vaish
I had recently committed a patch that removed the WakeUp*.py files from the slicc/ast directory. I had forgotten to remove the import calls for these files from slicc/ast/__init__.py. This resulted in error while running regressions on zizzer. This patch does the needful.
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type.
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode.
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19Ruby: dma retry fixBrad Beckmann
This patch fixes the problem where Ruby would fail to call sendRetry on ports after it nacked the port. This patch is particularly helpful for bursty dma requests which often include several packets.
2011-03-19RubyPort: minor fixes to trace flag and dprintfsBrad Beckmann
2011-03-19ruby: added useful dma progress dprintfBrad Beckmann
2011-03-19slicc: improved invalid transition messageBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type is used. For those data types for which code should be generated, the keyword structure is used. This patch eliminates the use of keyword external_type for defining structures. structure key word can now have an optional attribute external, which would be used for figuring out whether or not to generate the code for this structure. Also, now structures can have functions as well data members in them.
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_all_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-18swig: get rid of m5.internal.random module (swig/random.i)Steve Reinhardt
Thanks to swig this was interfering with the standard Python random module. The only function in that module was seed(), which erroneously called srand48(). Moved the function to m5.internal.core, renamed it seedRandom(), and made it call random_mt.init() instead.
2011-03-18base: disable FastAlloc in debug builds by defaultSteve Reinhardt
FastAlloc's reuse policies can mask allocation bugs, so we typically want it disabled when debugging. Set FORCE_FAST_ALLOC to enable even when debugging, and set NO_FAST_ALLOC to disable even in non-debug builds.
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
Updated some of the assembly code sequences to use armv7 instructions and coprocessor 15 for storing the TLS pointer.
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed.
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
Get rid of unused members and use base types rather than derrived values where possible to limit amount of state.
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever.
2011-03-17Ruby: minor bugfix, line did not adhere to some macro usage conventions.Lisa Hsu
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu
2011-03-11SCons: Stop embedding the mercurial revision into the binary.Gabe Black
This causes a lot of rebuilds that could have otherwise possibly been avoided, and, more annoyingly, a lot of unnecessary rerunning of the regressions. The benefits of having the revision in the output haven't materialized, so this change removes it.
2011-03-11Gems: Eliminate the now unused GEMS_ROOT scons variable.Gabe Black
2011-03-11Ruby: Get rid of the dead ruby tester.Gabe Black
None of the code in the ruby tester directory is compiled or referred to outside of that directory. This change eliminates it. If it's needed in the future, it can be revived from the history. In the mean time, this removes clutter and the only use of the GEMS_ROOT scons variable.
2011-03-08Alpha: Fix the datatypes of some values read from the simulated kernel.Yi Xiang
2011-03-03SCons: Clean up some inconsistent capitalization in scons options.Gabe Black
2011-03-02X86: Use the npc as the pc when doing a nativetrace, not what M5 considers ↵Gabe Black
the pc.
2011-03-02X86: Decode the mysterious and elusive ffreep x87 instruction.Gabe Black
The internet says this instruction was created by accident when an Intel CPU failed to decode x87 instructions properly. It's been documented on a few rare occasions and has generally worked to ensure backwards compatability. One source claims that the gcc toolchain is basically the only thing that emits it, and that emulators/binary translators like qemu and bochs implement it. We won't actually implement it here since we're hardly implementing any other x87 instructions either. If we were to implement it, it would behave the same as ffree but then also pop the register stack. http://www.pagetable.com/?p=16
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01X86: Mark IO reads and writes as non-speculative.Gabe Black
2011-03-01X86: Mark prefetches as such in their instruction and request flags.Gabe Black
2011-03-01Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBufferNilay Vaish
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs.
2011-03-01Ruby: Mention that Ruby's bound checking option only applies to Ruby.Gabe Black
2011-02-27X86: If PCI config space is disabled, pass through to regular IO addresses.Gabe Black
2011-02-27X86: Use regular read requests in the walker instead of read exclusive.Gabe Black