| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Trigger system calls from the SupervisorCall invoke method. | Gabe Black | |
| This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic. | |||
| 2010-06-02 | ARM: Fix multiply operations. | Gabe Black | |
| These fixes were provided by Ali and fix the saturation condition code and various multiply instructions. | |||
| 2010-06-02 | ARM: Decode the scalar saturating add/subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the parallel add and subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement signed saturating add and/or subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). | Gabe Black | |
| 2010-06-02 | ARM: Decode unconditional ARM instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ldm exception return writes back its base in the right mode. | Gabe Black | |
| This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end. | |||
| 2010-06-02 | ARM: Rework how unrecognized/unimplemented instructions are handled. | Gabe Black | |
| Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic. | |||
| 2010-06-02 | ARM: Add support for "SUBS PC, LR and related instructions". | Gabe Black | |
| 2010-06-02 | ARM: Make ldrs into the PC and ldm exception return do interworking branches. | Gabe Black | |
| 2010-06-02 | ARM: Align the PC when using it as the base for a load. | Gabe Black | |
| 2010-06-02 | ARM: Implement ADR as separate from ADD. | Gabe Black | |
| 2010-06-02 | ARM: Add support for interworking branch ALU instructions. | Gabe Black | |
| 2010-06-02 | ARM: Fix when the flag bits are updated for thumb. | Gabe Black | |
| 2010-06-02 | ARM: Don't rely on undefined behavior to get arithmetic right shift. | Gabe Black | |
| Shifting to the right of a signed value when the MSB is one is technically undefined behavior, even though in my experience it's done the "right thing" and sign extended the value. This replaces the arithmetic right shift code in ARM that uses that coincidence with some code that relies on bit math. | |||
| 2010-06-02 | ARM: Restrict the shift amount from a register to 8 bits. | Gabe Black | |
| The shift amount when taken from a register is supposed to be truncated to an 8 bit value. | |||
| 2010-06-02 | ARM: Define the VFP load/store multiple instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the VFP load/store multiple instructions. | Gabe Black | |
| 2010-06-02 | ARM: Fix the constant describing the number of floating point registers. | Gabe Black | |
| 2010-06-02 | ARM: Add templates for VFP load/store multiple instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add base classes for VFP load/store multiple. | Gabe Black | |
| 2010-06-02 | ARM: Add floating point load/store microops. | Gabe Black | |
| 2010-06-02 | ARM: Add an fp version of one of the microop indexed registers. | Gabe Black | |
| 2010-06-02 | ARM: Move the mmap region to where Linux actually has it. | Gabe Black | |
| 2010-06-02 | ARM: Eliminate the unused rhi and rlo operands. | Gabe Black | |
| 2010-06-02 | ARM: Move the macro mem constructor out of the isa desc. | Gabe Black | |
| This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code. | |||
| 2010-06-02 | ARM: Make macroops panic if executed directly. | Gabe Black | |
| The macroop should never be executed, only it's microops will. | |||
| 2010-06-02 | ARM: GCC < 4.3 has some issues with attribute no return on some functions. ↵ | Ali Saidi | |
| Fix so it works for older gccs. | |||
| 2010-06-02 | ARM: Split out the "basic" templates and format. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa | |||
| 2010-06-02 | ARM: Remove unnecessary cruft from includes.isa. | Gabe Black | |
| 2010-06-02 | ARM: Move the inst2string function out of the isa_desc. | Gabe Black | |
| Delete the now empty formats/util.isa. | |||
| 2010-06-02 | ARM: Get rid of the unused ArmGenericCodeSubs. | Gabe Black | |
| 2010-06-02 | ARM: Make the predecoder print out the ExtMachInst it gathered when traced. | Gabe Black | |
| 2010-06-02 | ARM: Remove special naming for the new version of multiply. | Gabe Black | |
| 2010-06-02 | ARM: Hook the new multiply instructions into all the decoders. | Gabe Black | |
| 2010-06-02 | ARM: Implement all integer multiply instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add templates for multiply instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add base classes for multiply instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode plain binary immediate thumb data processing instructions. | Gabe Black | |
| 2010-06-02 | ARM: Define a new "movt" data processing instruction. | Gabe Black | |
| 2010-06-02 | ARM: Hook the new branch instructions into the 32 bit thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Hook the new branch instructions into the 16 bit thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Eliminate the old style branch instructions. | Gabe Black | |
| 2010-06-02 | ARM: Hook the new branch instructions into the ARM decoder. | Gabe Black | |
| 2010-06-02 | ARM: Implement branch instructions external to the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add new templates for branch instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement new base classes for branches. | Gabe Black | |
| 2010-06-02 | ARM: Replace the interworking branch base class with a special operand. | Gabe Black | |
| 2010-06-02 | ARM: Fix PC operand handling. | Gabe Black | |
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