index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
Age
Commit message (
Expand
)
Author
2006-07-27
Clean up some more config stuff.
Kevin Lim
2006-07-27
Output the command line.
Kevin Lim
2006-07-27
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-27
Need config read/write latency.
Kevin Lim
2006-07-26
MIPS ISA runs 'hello world' in O3CPU ...
Korey Sewell
2006-07-26
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2006-07-26
Added alot of fp instructions, and some impdep instructions.
Gabe Black
2006-07-26
Now ignore sigaction
Gabe Black
2006-07-23
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell
2006-07-23
This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...
Korey Sewell
2006-07-23
Added myself to the authors list.
Gabe Black
2006-07-22
Fixed subtract with carry, and started some work with floating point.
Gabe Black
2006-07-21
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-21
Minor functionality updates.
Kevin Lim
2006-07-20
Fixed a glitch in the disassembly output.
Gabe Black
2006-07-20
Merge m5.eecs.umich.edu:/bk/newmem
Gabe Black
2006-07-20
Merge zizzer:/bk/newmem
Ali Saidi
2006-07-20
Move PioPort timing code into Simple Timing Port object
Ali Saidi
2006-07-20
Enforce the timing cpu ticking at it's clock rate
Ali Saidi
2006-07-19
Merge zizzer:/bk/newmem
Ali Saidi
2006-07-19
Change the device latency here to a latency rather than a Tick
Ali Saidi
2006-07-19
Minor changes to reflect state used for regression stats.
Kevin Lim
2006-07-19
Put regression tests back into m5. They are located in the "tests" directory...
Kevin Lim
2006-07-19
Get the path to load the ini file from. I'm not sure if this fix is needed i...
Kevin Lim
2006-07-19
O3CPU fixes.
Kevin Lim
2006-07-19
Some minor compiling fixes.
Kevin Lim
2006-07-19
Cleaned things up a little.
Gabe Black
2006-07-18
Merge m5.eecs.umich.edu:/bk/newmem
Gabe Black
2006-07-14
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-14
Minor updates.
Kevin Lim
2006-07-14
Fix the CheckerCPU being included via python.
Kevin Lim
2006-07-14
forgot tid
Korey Sewell
2006-07-14
For now, halt context is the same as deallocating.
Korey Sewell
2006-07-14
MIPS specific fixes ... the main thing is that SMT threads get their own stac...
Korey Sewell
2006-07-13
Merge zizzer:/bk/newmem
Ali Saidi
2006-07-13
fix help when no arguments are passed to m5
Ali Saidi
2006-07-13
add system.mem_mode = ['timing', 'atomic']
Ali Saidi
2006-07-13
Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...
Kevin Lim
2006-07-13
Fix for bug when squashing and the fetching. Now fetch checks if the cache d...
Kevin Lim
2006-07-13
Update for changes to draining.
Kevin Lim
2006-07-13
Fix help message printing. Might need to clean up the handling of the sys.ex...
Kevin Lim
2006-07-12
memory mode information now contained in system object
Ali Saidi
2006-07-12
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-12
Be sure to include the EIO sources as well so we can run regression tests.
Kevin Lim
2006-07-12
Serialization changes to make O3CPU consistent with the other models.
Kevin Lim
2006-07-12
Push more default options to the Python object level as they are rarely chang...
Kevin Lim
2006-07-12
Updates for serialization. As long as the tickEvent doesn't need to be seria...
Kevin Lim
2006-07-12
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-12
Track the PC of the cache data stored in fetch so it doesn't access memory mu...
Kevin Lim
2006-07-12
Add --pdb
Nathan Binkert
[prev]
[next]